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One Hat Cyber Team
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Linux host.raqmix.cloud 6.8.0-1025-azure #30~22.04.1-Ubuntu SMP Wed Mar 12 15:28:20 UTC 2025 x86_64
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qed
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qed_init_values_zipped-8.15.3.0.bin
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X Y ! @ A B C D Z E F G H I J K % $ L M N O P Q 0 1 R S [ T \ K l m h i < = @ N O b n > ? A P Q ` o c p T ] f g ^ _ ] ^ _ ` a b c d e f g [ \ h i j k l m ; U V W 7 ) * + X Y # " , j - k . R / S ( L 2 M Z d 8 e 9 F : B 3 E 4 G 5 H 6 I J D C ! " # $ & ' ' /' D' Z' l' & ~' ' ' ' ' ' ' ( ,( G( b( }( ( ( & ( ( ( ( ) () >) T) t) ) ) ) ) ) ) ) * * * .* ?* Q* \* q* * * * * * * * + + &+ 8+ J+ \+ n+ + + + + + + + + , ", Z' 4, H, \, p, , , , , , & , , - %- :- U- p- z- - - - - * * 8+ ", * * , l' Z' &+ J+ & - - - - . !. 8. J. a. z. . . . . . . . / / 0/ E/ _/ y/ / / / / / 0 0 ,0 ?0 R0 g0 0 0 0 0 0 0 1 &1 :1 N1 a1 t1 1 1 1 1 1 2 2 22 H2 \2 p2 2 2 2 2 2 2 3 '3 >3 T3 j3 ~3 3 3 3 3 3 4 .4 E4 ]4 u4 4 4 4 4 4 5 (5 @5 W5 n5 5 5 5 5 5 6 "6 96 U6 q6 6 6 6 6 6 7 7 07 K7 b7 y7 7 7 7 7 7 8 8 18 C8 Z8 r8 8 8 8 8 8 9 %9 79 N9 f9 }9 9 9 9 9 : : +: B: Z: q: : : : : : ; ; 6; N; e; |; ; ; ; ; < !< 8< P< g< ~< < < < < = = ,= D= [= r= = = = = = > > 0> C> V> i> |> > > > > > ? ? 7? M? c? w? ? ? ? ? ? ? @ )@ B@ Y@ o@ @ @ @ @ @ @ A A 0A KA dA {A A A A A A A B $B >B RB mB B B B B B B C C ,C FC `C tC C C C C C C D &D 9D ND hD D D D D D D E !E 5E TE uE E E E E E F F 5F NF gF F F F F F F G ?G `G wG G G G G H H ,H >H PH q* bH vH H H H H H H I I *I >I RI fI zI I I I I I I I J J 2J DJ VJ hJ zJ J J J J J J J K K .K @K RK dK vK K + * & K K K K K L L #L 2L KL ]L xL L L L L L L L >I RI * * 8+ ", , l' bH fI H H I L M "M 6M JM ^M rM M M bH M M M M I &+ Z' l' * * 8+ & M N !N 3N EN WN mN N N N N N N O O 'O CO q* ", * 8+ l' Z' , * &+ * * \+ + + + + J+ n+ & OO cO uO O & O O & O O O O q* O O P #P 7P KP _P sP P I dK P P RK P P P * , , * * * * J+ + + + l' Z' &+ 8+ ", \+ & P Q Q )Q <Q QQ dQ wQ Q Q Q Q Q Q Q & R R ,R 9R FR TR cR rR R R R R R R R R R S q* vH , S 1S ES YS mS S S S S S S S T !T 5T IT ]T qT T T T T T T T U %U 9U MU aU uU U U U U U U V V )V =V QV eV yV V V V V V V W W -W AW UW iW }W W W W W W W X X 1X EX YX mX X X X + X JM ^M X X X Y !Y 5Y L M "M 6M IY ]Y qY Y Y Y Y Y Y Y Z %Z 9Z MZ aZ uZ Z 4, H, \, p, , Z Z Z & Z P Q Q )Q Q QQ dQ Z wQ Z Q Q Q Q Q Q [ #[ 6[ I[ & Z[ l[ |[ [ [ [ [ [ [ [ [ \ \ 2\ RI fI bH ", * * Z' l' * * 8+ & I\ & U\ l' , Z' & d\ y\ \ \ \ \ \ O + ", , l' Z' &+ 8+ * * \+ * + + + + J+ * & \ \ ] "] 4] E] W] h] z] ] ] ] ] ] ] ] ] ^ !^ 2^ D^ U^ g^ x^ ^ ^ ^ ^ ^ ^ ^ _ !_ 5_ L_ b_ x_ _ _ _ _ _ _ ` ` 1` G` ]` s` + + + \+ n+ * + J+ + + + P P * &+ * ", + + T T * P ` ` ` ` , * + * , l' & \ \ ` ` a a 'a 8a Ja [a ma ~a W] h] ] ] ] ^ !^ 2^ D^ U^ g^ x^ ^ ^ ^ ^ ^ ^ ^ _ !_ 5_ L_ b_ x_ _ _ _ a >I ` ` 1` G` a a _ n+ + \+ + + + + J+ + + + P P P &+ + ", * * T T * * * , l' & \ \ a a a a 'a 8a a b b 'b 9b Jb \b mb z] ] ] ] ] ] ] ^ !^ 2^ D^ U^ g^ x^ ^ ^ ^ ^ ^ ^ ^ _ !_ 5_ L_ b_ x_ _ _ _ b 1` G` ]` s` P b b vH b b a + + + + + * + + \+ n+ RK P P ", , * P * X X J+ + Z' &+ , l' & \ \ ` ` a a a a 'a 8a 4] E] ma ~a W] h] z] ] ] ] ] ] ] ^ !^ 2^ D^ U^ g^ x^ ^ ^ ^ ^ ^ ^ ^ _ !_ _ b c $c ?c Yc qc c c c _ _ c c RI c d 'd , + * P * P P n+ + * + + + + I I I 8+ vK P ", + ;d Od ed {d K dK \+ P * * * * J+ + + + , l' & \ \ ` ` a a d d 4] E] ma ~a ] ] ] ^ !^ 2^ D^ U^ g^ x^ ^ ^ ^ ^ ^ _ !_ 5_ L_ b_ x_ _ _ _ d _ _ ` ` _P 1` G` a a + + n+ \+ + + J+ + + + P P P &+ + ", , + T T * _ ` ` KP ]` s` * * + * * , l' & \ \ d d ] ] D^ U^ g^ x^ ^ ^ ^ ^ ^ _ !_ _ _ H d d * * ", l' Z' &+ 8+ + + J+ * , H e +e * & Ae Le Ze ie xe e e e e e e e f f 6f Bf ff f f f f g *g 7g Dg Qg \g fg sg zg g g M M 1` G` H I K I I I J J K K J J .K @K g g I I g g RK P P P dK vK J zJ J J J J VJ hJ 2J DJ P &+ Z' J+ n+ \+ + + + + + + + * , * + + * T T T T T T T U %U g h h 4h Ih ^h sh * , P l' * * & h h h h h h i (i >i Qi di wi i i i i i i j $j :j Qj hj |j j j j j j j k &k @k Xk hk xk k k k k k k l "l >I \+ * * * * + + + &+ 8+ ", J+ , l' & 8l @l Sl cl zl l l l q* *I , Z' &+ 8+ ", & - l l l - - m m +m - . @m Rm dm !. 8. ym m m J. a. m z. . . . m . m m . n . . / !n 0/ E/ _/ y/ / / / / / 0 0 ,0 ?0 4n R0 g0 0 0 0 0 0 0 1 &1 :1 N1 a1 Gn t1 1 1 1 1 1 2 2 22 H2 \2 p2 2 Zn 2 2 2 2 2 3 '3 >3 T3 j3 ~3 3 3 3 3 3 4 .4 E4 ]4 u4 4 4 4 4 4 5 (5 @5 W5 n5 5 5 5 5 5 6 "6 96 U6 q6 6 6 6 6 6 7 mn {n 7 07 K7 b7 y7 7 7 18 n n n C8 Z8 r8 8 8 8 8 8 9 %9 ; = > > 0> i> |> > > > > > ? ? 7? M? c? w? ? ? ? ? ? ? @ )@ B@ Y@ o@ @ @ @ @ @ @ A A 0A KA dA {A A A A A A A B $B >B RB mB B B B B B 9D n n n o 9o Vo so o o o o p )p Jp kp p p p p p q q /q Bq Uq hq H ,H >H PH q* bH vH H H H H H H I I *I >I RI fI zI I {q q J J K K .K @K I I g g g g q VJ hJ zJ J J J J J J J 2J DJ I q q q P P P RK I I dK vK K n+ + + + + * * + P , * P + & q q r H H I O 7P KP _ d g DJ 2J I RK dK vK K P P P P * P I I @K I J J I g * H H H I , + + + + n+ + 8+ \+ * + * + + ", J+ Z' &+ * + + J K K .K hJ zJ J J J J J J g VJ l' , * & r %r 6r Gr Vr kr r r r r r r s s 1s Gs as ws s s s s s s s s t * * * ", 8+ l' * , Z' &+ * * * ", 8+ l' J+ , Z' &+ * * * * ", Z' * l' &+ 8+ , * * ", 8+ l' * , Z' &+ & #t 2t Ct Rt et xt t t t t t t u u ,u 5u Gu Vu pu u u u u u u v (v ;v Jv \v jv }v v v v v v v w &w 8w Hw Yw mw w w w 1` G` &+ l' Z' , + * * + + + + fI *I ", * w w w M M 8+ l' &+ Z' , + * * + + + + & w w w w x x (x 7x Fx Ux dx *I bH Z' &+ & sx ~x x x x zI *I Z' &+ * * 8+ , fI bH vH I l' Z' * * &+ ", , l' 8+ ", &+ Z' RI zI , l' * * Z' 8+ * & x x x x y y %y 4y Cy Ry q* H H H #P &+ + \+ n+ * * * + J+ Z' l' 8+ * ", * , * + + I 7P + + + + & ay x ky wy y y y y & - l - - m - . Rm !. 8. m J. a. z. . . y . / / !n 0/ E/ _/ y/ / / / / 0 0 y y z z <z 3 3 3 3 3 4 .4 E4 ]4 u4 4 4 4 4 4 5 (5 @5 W5 n5 5 5 5 5 5 6 "6 96 U6 q6 6 6 7 7 07 K7 b7 y7 7 7 7 7 7 18 n C8 Z8 r8 8 8 8 8 8 9 %9 Wz 79 N9 f9 }9 9 9 9 9 : : iz +: B: Z: q: : : : : : ; {z ; 6; N; e; |; ; ; ; ; {A 9D z z H H ,H >H PH q* bH vH H H H H H H I I *I >I RI fI zI I RK vK dK P P + * * + + , * P P P q* z z {d >I O e +e l "l z z { ){ ?{ U{ k{ { { { { { { | I I I dK P P P P * * + + , l' ", * 8+ &+ P , * + \+ n+ * J+ * + + I K vK + + + & !| /| @| M| \| k| x| | q* fI H H H , Z' l' ", * * &+ & | | | | | | } , &+ l' 8+ Z' & } "} /} <} Y} v} } bH Z' "} /} <} Y} v} } l' , & } } } } ~ ~ 4~ Q~ c~ z~ q H + \+ n+ + + , 4, H, L M "M Z' 8+ UW iW ~ ~ ~ * X X ~ rM M J+ + + + Z Z Z l' T T T ", 1X EX V V & ~ ~ ! 5 N _ l zI *I RI 8+ * * * * J+ Z Z l' &+ & & ' ? X o ˀ ڀ % 4 C R a q Ё ߁ * 9 H W g w ̂ 3 H ^ t ̃ " ; P e ~ ̄ 4 N k ߅ 6 S h | φ & < R h ~ ׇ 4 N h Ј $ A ^ { ҉ , A V k ؊ 0 F Z s Ћ 8 R l 4 Q n ȍ ݍ 2 H ^ t ̎ $ 9 R l ԏ " ? \ y А - ' 9 K ] o ɑ ۑ K g g g q q q q q {q K .K @K I I g vK hJ J J # 5 G Y k , * * * J+ + + + + \+ l' Z' &+ 8+ ", * } zJ J J J J J K I I I I J J 2J DJ VJ Œ ג * P P P n+ + 1 C U g y P P RK dK + + + * ӓ * + + , n+ + + + + * * + , * * * J+ + + + + \+ l' Z' &+ 8+ ", * & # 4 G T c q Ŕ Ӕ & ( 7 E T _ k v + P K DJ * P I zJ + P I J + , dK J n+ + RK J + P I VJ + * vK 2J * P I hJ .K I g g @K I g g * * J+ + + + + \+ , l' Z' &+ 8+ ", * * J J J J J K J K q q {q q q q & Ǖ ޕ " 8 N d y Ֆ - B Y p ʗ " 9 P g } Z' , &+ l' & Ԙ ܘ MISC: interrupt status 0 is not 0. MISC_REG_INT_STS AEU: IGU: AFTER_INVERT_1 is not 0 MISC_REG_AEU_AFTER_INVERT_1_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_2 is not 0x90 MISC_REG_AEU_AFTER_INVERT_2_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_3 is not 0 MISC_REG_AEU_AFTER_INVERT_3_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_4 is not 0 MISC_REG_AEU_AFTER_INVERT_4_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_5 is not 0 MISC_REG_AEU_AFTER_INVERT_5_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_6 is not 0 MISC_REG_AEU_AFTER_INVERT_6_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_7 is not 0 MISC_REG_AEU_AFTER_INVERT_7_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_8 is not 0x34000000 MISC_REG_AEU_AFTER_INVERT_8_IGU MISC_REG_ATTN_NUM_ST AEU: IGU: AFTER_INVERT_9 is not 0x60 MISC_REG_AEU_AFTER_INVERT_9_IGU MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_1 is not 0 MISC_REG_AEU_AFTER_INVERT_1_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_2 is not 0x90 MISC_REG_AEU_AFTER_INVERT_2_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_3 is not 0 MISC_REG_AEU_AFTER_INVERT_3_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_4 is not 0 MISC_REG_AEU_AFTER_INVERT_4_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_5 is not 0 MISC_REG_AEU_AFTER_INVERT_5_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_6 is not 0 MISC_REG_AEU_AFTER_INVERT_6_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_7 is not 0 MISC_REG_AEU_AFTER_INVERT_7_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_8 is not 0x34000000 MISC_REG_AEU_AFTER_INVERT_8_MCP MISC_REG_ATTN_NUM_ST AEU: MCP AFTER_INVERT_9 is not 0x60 MISC_REG_AEU_AFTER_INVERT_9_MCP MISC_REG_ATTN_NUM_ST MISC: system kill occurred; MISC_REG_AEU_SYS_KILL_OCCURRED MISCS: interrupt status 0 is not 0. MISCS_REG_INT_STS_0 MISCS: pcie_rst_b was asserted without perst assertion MISCS_REG_PCIE_HOT_RESET DMAE: command 0 go is not 0 DMAE_REG_GO_C0 DMAE: command 1 go is not 0 DMAE_REG_GO_C1 DMAE: command 2 go is not 0 DMAE_REG_GO_C2 DMAE: command 3 go is not 0 DMAE_REG_GO_C3 DMAE: command 4 go is not 0 DMAE_REG_GO_C4 DMAE: command 5 go is not 0 DMAE_REG_GO_C5 DMAE: command 6 go is not 0 DMAE_REG_GO_C6 DMAE: command 7 go is not 0 DMAE_REG_GO_C7 DMAE: command 8 go is not 0 DMAE_REG_GO_C8 DMAE: command 9 go is not 0 DMAE_REG_GO_C9 DMAE: command 10 go is not 0 DMAE_REG_GO_C10 DMAE: command 11 go is not 0 DMAE_REG_GO_C11 DMAE: command 12 go is not 0 DMAE_REG_GO_C12 DMAE: command 13 go is not 0 DMAE_REG_GO_C13 DMAE: command 14 go is not 0 DMAE_REG_GO_C14 DMAE: command 15 go is not 0 DMAE_REG_GO_C15 DMAE: command 16 go is not 0 DMAE_REG_GO_C16 DMAE: command 17 go is not 0 DMAE_REG_GO_C17 DMAE: command 18 go is not 0 DMAE_REG_GO_C18 DMAE: command 19 go is not 0 DMAE_REG_GO_C19 DMAE: command 20 go is not 0 DMAE_REG_GO_C20 DMAE: command 21 go is not 0 DMAE_REG_GO_C21 DMAE: command 22 go is not 0 DMAE_REG_GO_C22 DMAE: command 23 go is not 0 DMAE_REG_GO_C23 DMAE: command 24 go is not 0 DMAE_REG_GO_C24 DMAE: command 25 go is not 0 DMAE_REG_GO_C25 DMAE: command 26 go is not 0 DMAE_REG_GO_C26 DMAE: command 27 go is not 0 DMAE_REG_GO_C27 DMAE: command 28 go is not 0 DMAE_REG_GO_C28 DMAE: command 29 go is not 0 DMAE_REG_GO_C29 DMAE: command 30 go is not 0 DMAE_REG_GO_C30 DMAE: command 31 go is not 0 DMAE_REG_GO_C31 DMAE: Parity status is not 0 DMAE_REG_PRTY_STS_H_0 DBG: Parity status is not 0 DBG_REG_PRTY_STS_H_0 GRC: GRC_REG_TRACE_FIFO_VALID_DATA = 1, the trace FIFO contains at least one valid data. GRC_REG_TRACE_FIFO_VALID_DATA GRC: GRC_REG_INT_STS_0, one of the interrupts is set, bits 3:0: path_isolation_error, global_reserved_address, timeout_event, address_error. GRC: There is an interrupt on register 0 GRC_REG_INT_STS_0 GRC: Parity status is not 0 GRC_REG_PRTY_STS_H_0 OPTE: Parity status is not 0 OPTE_REG_PRTY_STS_H_0 DORQ: Interrupt Status is not 0 DORQ: There is an interrupt on register 0 DORQ_REG_INT_STS DORQ: Parity status is not 0 DORQ_REG_PRTY_STS_H_0 DORQ: Credit to XCM is different than default value DORQ: There are pending messages in DORQ->XCM interface DORQ_REG_XCM_MSG_INIT_CRD DORQ: Credit to TCM is different than default value DORQ: There are pending messages in DORQ->TCM interface DORQ_REG_TCM_MSG_INIT_CRD DORQ: Credit to UCM is different than default value DORQ: There are pending messages in DORQ->UCM interface DORQ_REG_UCM_MSG_INIT_CRD DORQ: Credit to PBF is different than default value DORQ: There are pending messages in DORQ->PBF interface DORQ_REG_PBF_CMD_INIT_CRD DORQ: PF Usage counter is not 0 DORQ: There are currently doorbells pending on the PF DORQ_REG_PF_USAGE_CNT DORQ: VF Usage counter is not 0 DORQ: There are currently doorbells pending on the VF DORQ_REG_VF_USAGE_CNT DORQ: CFC load request FIFO current fill level is not 0 DORQ: There are pending messages in DORQ->CCFC interface DORQ_REG_CFC_LD_REQ_FIFO_FILL_LVL DORQ: DORQ FIFO is not empty DORQ: There are currently doorbells pending DORQ_REG_DORQ_FIFO_FILL_LVL DORQ: Doorbell drops counter is not 0 DORQ: there were doorbell drops DORQ_REG_DB_DROP_CNT DORQ_REG_DB_DROP_DETAILS DORQ_REG_DB_DROP_DETAILS_REASON DORQ: Doorbell aborts counter is not 0 DORQ: there were doorbell aborts DORQ_REG_DPM_ABORT_CNT DORQ_REG_DPM_ABORT_REASON DORQ_REG_DPM_ABORT_DETAILS_REASON DORQ: DPM Table current fill level is not 0 DORQ: There are DPMs currently in process DORQ_REG_DPM_TBL_FILL_LVL IGU: CAM Parity status is not 0 IGU_REG_PRTY_STS IGU: Parity status 0 is not 0 IGU_REG_PRTY_STS_H_0 IGU attention message write done pending is not empty IGU: attention write done pending IGU_REG_ATTN_WRITE_DONE_PENDING IGU: block is not in idle. Some interrupts are asserted IGU_REG_INTERRUPT_STATUS IGU: some unauthorized commands arrived to the IGU. Use igu_dump_fifo utility for more details. IGU_REG_ERROR_HANDLING_DATA_VALID Some messages were not executed in the IGU. IGU: Commands were dropped IGU_REG_SILENT_DROP IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state IGU_REG_SB_CTRL_FSM IGU: block is not in idle. INT_HANDLE_FSM should be zero in idle state IGU_REG_INT_HANDLE_FSM IGU: block is not in idle. SB_ATTN_FSM should be zero or two in idle state IGU_REG_ATTN_FSM IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state IGU_REG_CTRL_FSM IGU: block is not in idle. SB_ARB_FSM should be zero in idle state IGU_REG_PXP_ARB_FSM CAU: Parity status is not 0 CAU_REG_PRTY_STS_H_0 CAU: Block is not in idle CAU: Pending IGU Request CAU_REG_IGU_REQ_CREDIT_STATUS CAU: Block is not in idle CAU: Pending IGU Command CAU_REG_IGU_CMD_CREDIT_STATUS CAU: Block is not in idle CAU: FIFOs are not empty CAU_REG_DEBUG_FIFO_STATUS CAU: Fatal unauthorized command arrived from PXP Invalid command arrived to CAU from PXP switch CAU_REG_ERROR_PXP_REQ CAU: Fatal. CAU arrived to invalid FSM line. CAU_REG_ERROR_FSM_LINE CAU_REG_ERROR_FSM_LINE_PRE CAU: Fatal parity error occurred in CAU CAU_REG_PARITY_LATCH_STATUS CAU: Fatal unauthorized cleanup command arrived from GRC CAU_REG_ERROR_CLEANUP_CMD_REG CAU: Block is not in idle CAU: Agg Unit is not in idle CAU_REG_AGG_UNITS_0TO15_STATE CAU: Block is not in idle CAU: Agg Unit is not in idle CAU_REG_AGG_UNITS_16TO31_STATE CAU: Block is not in idle CAU: Agg Unit is not in idle CAU_REG_AGG_UNITS_32TO47_STATE CAU: Block is not in idle CAU: Agg Unit is not in idle CAU_REG_AGG_UNITS_48TO63_STATE CAU: Block is not in idle CAU: Not all WDones were received from IGU CAU_REG_REQ_COUNTER CAU_REG_WDONE_COUNTER CAU: Block is not in idle CAU: Not all ACKs were received from IGU CAU_REG_REQ_COUNTER CAU_REG_ACK_COUNTER CAU: Block is not in idle CAU: Main FSM is not idle CAU_REG_MAIN_FSM_STATUS CAU: Block is not in idle CAU: Var Read FSM is not idle CAU_REG_VAR_READ_FSM_STATUS CAU: Block is not in idle CAU: IGU DMA FSM is not idle CAU_REG_IGU_DMA_FSM_STATUS CAU: Block is not in idle CAU: IGU CQE AMD FSM is not idle CAU_REG_IGU_CQE_CMD_FSM_STATUS CAU: Block is not in idle CAU: IGU CQE AGG FSM is not idle CAU_REG_IGU_CQE_AGG_FSM_STATUS PRS: Interrupt Status is not 0 PRS: Fatal error PRS_REG_INT_STS_0 PRS_REG_MINI_CACHE_FAILED_RESPONSE PRS_REG_MINI_CACHE_ENTRY GRC_REG_TRACE_FIFO_VALID_DATA PRS: CAM Parity status is not 0 PRS_REG_PRTY_STS PRS: Parity status 0 is not 0 PRS_REG_PRTY_STS_H_0 PRS: Parity status 1 is not 0 PRS_REG_PRTY_STS_H_1 PRS: The number of packets in the parser pipeline is not 0 PRS: There are outstanding packets in the PRS pipeline PRS_REG_PRS_PKT_CT PRS: The number of available packets waiting for Parser processing is not 0 There are available packets waiting for PRS processing. 16:8 - Loopback TCs, 7:0 - main TCs PRS_REG_QUEUE_PKT_AVAIL_STATUS PRS: There are traffic-classes that are backpressured by the STORM PRS: There are traffic-classes that are blocked by the STORM. Each set bit represents a blocked TC (7-0) from MSDM, TSDM, and USDM, respectively. PRS_REG_STORM_BKPRS_STATUS PRS: BRB has asserted Stop Parsing indication to PRS PRS: The number of outstanding packets in the pipeline is above a threshold so PRS stopped processing new packets PRS_REG_STOP_PARSING_STATUS PRS: TCM Credit Count is not 0 PRS: There are TCM messages that were not ACKed PRS_REG_TCM_CURRENT_CREDIT PRS: CCFC Search Credit Count is not 0 PRS: There are CCFC search requests that were not ACKed PRS_REG_CCFC_SEARCH_CURRENT_CREDIT PRS: TCFC Search Credit Count is not 0 PRS: There are TCFC search requests that were not ACKed PRS_REG_TCFC_SEARCH_CURRENT_CREDIT PRS: CCFC Load Credit Count is not 0 PRS: There are CCFC load requests that were not ACKed PRS_REG_CCFC_LOAD_CURRENT_CREDIT PRS: TCFC Load Credit Count is not 0 PRS: There are TCFC load requests that were not ACKed PRS_REG_TCFC_LOAD_CURRENT_CREDIT PRS: The number of outstanding CCFC search requests is not 0 PRS: There are outstanding CCFC search requests PRS_REG_CCFC_SEARCH_REQ_CT PRS: The number of outstanding TCFC search requests is not 0 PRS: There are outstanding TCFC search requests PRS_REG_TCFC_SEARCH_REQ_CT PRS: The number of outstanding CCFC load requests is not 0 PRS: There are outstanding CCFC load requests PRS_REG_CCFC_LOAD_REQ_CT PRS: The number of outstanding TCFC load requests is not 0 PRS: There are outstanding TCFC load requests PRS_REG_TCFC_LOAD_REQ_CT PRS: The number of outstanding BRB SOP requests is not 0 PRS: There are outstanding BRB SOP requests PRS_REG_SOP_REQ_CT PRS: The number of outstanding BRB EOP requests is not 0 PRS: There are outstanding BRB EOP requests PRS_REG_EOP_REQ_CT PRM: Interrupt status is not 0 PRM_REG_INT_STS PRM: Parity status is not 0 PRM_REG_PRTY_STS_H_0 RSS: RSS_INIT_DONE is not 1 RSS: Block is not initialized RSS_REG_RSS_INIT_DONE RSS: Interrupt status is set RSS_REG_INT_STS RSS: Parity status is not 0 RSS_REG_PRTY_STS_H_0 RSS: RSS-TMLD interface credits != 0x20 RSS: Pending messages in RSS-TMLD interface RSS_REG_TMLD_CREDIT RSS: FIFOS are not empty RSS_REG_EMPTY_STATUS RSS: FIFOS are full RSS_REG_FULL_STATUS RSS: Counters are not 0 RSS_REG_COUNTERS_STATUS RSS: State machines are not in reset state RSS_REG_STATE_MACHINES PSWRQ2: rq_rbc_done is not 1 PSWRQ2: Block is not initialized PSWRQ2_REG_RBC_DONE PSWRQ2: rq_cfg_done is not 1 PSWRQ2: Block is not initialized PSWRQ2_REG_CFG_DONE PSWRQ2: Interrupt status is not 0 PSWRQ2_REG_INT_STS PSWRQ2: Parity status is not 0 PSWRQ2_REG_PRTY_STS_H_0 PSWRQ2: VQ is not empty PSWRQ2_REG_VQ0_ENTRY_CNT PSWRQ2: There are used credits on PSWRQ - PGLUE request interface. PSWRQ2_REG_BW_CREDIT PSWRQ2: TREQ FIFO is not empty PSWRQ2_REG_TREQ_FIFO_FILL_LVL PSWRQ2: ICPL FIFO is not empty PSWRQ2_REG_ICPL_FIFO_FILL_LVL PSWRQ: L2P error. Address(31:0) is not 0 PSWRQ2_REG_L2P_ERR_ADD_31_0 PSWRQ: L2P error. Address(63:23) is not 0 PSWRQ2_REG_L2P_ERR_ADD_63_32 PSWRQ: L2P error. Error details register is not 0. (12:0) - Length in bytes. (16:13) - PFID. (17) - VF_VALID. (25:18) - VFID. PSWRQ2_REG_L2P_ERR_DETAILS PSWRQ: L2P error. Error details register 2 is not 0. (15:0) - Request ID. (20:16) - client ID. (21) - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. (22) - w_nr - 0 - read; 1 - write.(27:23) - VQID. (28) - valid bit. PSWRQ2_REG_L2P_ERR_DETAILS2 PSWRQ2: There are more than four used SRs PSWRQ2_REG_SR_CNT PSWRQ2_REG_SR_NUM_CFG PSWRQ2: sr_cnt is not equal to sr_num_cfg PSWRQ2_REG_SR_CNT PSWRQ2_REG_SR_NUM_CFG PSWRQ2: SR_CNT_per_vq0 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_0 PSWRQ2_REG_MAX_SRS_VQ0 PSWRQ2: SR_CNT_per_vq1 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_1 PSWRQ2_REG_MAX_SRS_VQ1 PSWRQ2: SR_CNT_per_vq2 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_2 PSWRQ2_REG_MAX_SRS_VQ2 PSWRQ2: SR_CNT_per_vq3 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_3 PSWRQ2_REG_MAX_SRS_VQ3 PSWRQ2: SR_CNT_per_vq4 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_4 PSWRQ2_REG_MAX_SRS_VQ4 PSWRQ2: SR_CNT_per_vq5 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_5 PSWRQ2_REG_MAX_SRS_VQ5 PSWRQ2: SR_CNT_per_vq6 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_6 PSWRQ2_REG_MAX_SRS_VQ6 PSWRQ2: SR_CNT_per_vq9 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_9 PSWRQ2_REG_MAX_SRS_VQ9 PSWRQ2: SR_CNT_per_vq11 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_11 PSWRQ2_REG_MAX_SRS_VQ11 PSWRQ2: SR_CNT_per_vq12 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_12 PSWRQ2_REG_MAX_SRS_VQ12 PSWRQ2: SR_CNT_per_vq15 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_15 PSWRQ2_REG_MAX_SRS_VQ15 PSWRQ2: SR_CNT_per_vq16 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_16 PSWRQ2_REG_MAX_SRS_VQ16 PSWRQ2: SR_CNT_per_vq17 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_17 PSWRQ2_REG_MAX_SRS_VQ17 PSWRQ2: SR_CNT_per_vq18 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_18 PSWRQ2_REG_MAX_SRS_VQ18 PSWRQ2: SR_CNT_per_vq19 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_19 PSWRQ2_REG_MAX_SRS_VQ19 PSWRQ2: SR_CNT_per_vq21 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_21 PSWRQ2_REG_MAX_SRS_VQ21 PSWRQ2: SR_CNT_per_vq22 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_22 PSWRQ2_REG_MAX_SRS_VQ22 PSWRQ2: SR_CNT_per_vq23 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_23 PSWRQ2_REG_MAX_SRS_VQ23 PSWRQ2: SR_CNT_per_vq24 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_24 PSWRQ2_REG_MAX_SRS_VQ24 PSWRQ2: SR_CNT_per_vq26 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_26 PSWRQ2_REG_MAX_SRS_VQ26 PSWRQ2: SR_CNT_per_vq28 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_28 PSWRQ2_REG_MAX_SRS_VQ28 PSWRQ2: SR_CNT_per_vq29 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_29 PSWRQ2_REG_MAX_SRS_VQ29 PSWRQ2: SR_CNT_per_vq30 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_30 PSWRQ2_REG_MAX_SRS_VQ30 PSWRQ2: blk_cnt is not equal to blk_num_cfg PSWRQ2_REG_BLK_CNT PSWRQ2_REG_BLK_NUM_CFG PSWRQ2: There are more than eight used blocks PSWRQ2_REG_BLK_CNT PSWRQ2_REG_BLK_NUM_CFG PSWRQ2: blk_cnt_per_vq0 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_0 PSWRQ2_REG_MAX_BLKS_VQ0 PSWRQ2: blk_cnt_per_vq1 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_1 PSWRQ2_REG_MAX_BLKS_VQ1 PSWRQ2: blk_cnt_per_vq2 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_2 PSWRQ2_REG_MAX_BLKS_VQ2 PSWRQ2: blk_cnt_per_vq3 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_3 PSWRQ2_REG_MAX_BLKS_VQ3 PSWRQ2: blk_cnt_per_vq4 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_4 PSWRQ2_REG_MAX_BLKS_VQ4 PSWRQ2: blk_cnt_per_vq5 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_5 PSWRQ2_REG_MAX_BLKS_VQ5 PSWRQ2: blk_cnt_per_vq6 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_6 PSWRQ2_REG_MAX_BLKS_VQ6 PSWRQ2: blk_cnt_per_vq9 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_9 PSWRQ2_REG_MAX_BLKS_VQ9 PSWRQ2: blk_cnt_per_vq11 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_11 PSWRQ2_REG_MAX_BLKS_VQ11 PSWRQ2: blk_cnt_per_vq12 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_12 PSWRQ2_REG_MAX_BLKS_VQ12 PSWRQ2: blk_cnt_per_vq15 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_15 PSWRQ2_REG_MAX_BLKS_VQ15 PSWRQ2: blk_cnt_per_vq16 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_16 PSWRQ2_REG_MAX_BLKS_VQ16 PSWRQ2: blk_cnt_per_vq17 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_17 PSWRQ2_REG_MAX_BLKS_VQ17 PSWRQ2: blk_cnt_per_vq18 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_18 PSWRQ2_REG_MAX_BLKS_VQ18 PSWRQ2: blk_cnt_per_vq19 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_19 PSWRQ2_REG_MAX_BLKS_VQ19 PSWRQ2: blk_cnt_per_vq21 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_21 PSWRQ2_REG_MAX_BLKS_VQ21 PSWRQ2: blk_cnt_per_vq22 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_22 PSWRQ2_REG_MAX_BLKS_VQ22 PSWRQ2: blk_cnt_per_vq23 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_23 PSWRQ2_REG_MAX_BLKS_VQ23 PSWRQ2: blk_cnt_per_vq24 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_24 PSWRQ2_REG_MAX_BLKS_VQ24 PSWRQ2: blk_cnt_per_vq26 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_26 PSWRQ2_REG_MAX_BLKS_VQ26 PSWRQ2: blk_cnt_per_vq28 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_28 PSWRQ2_REG_MAX_BLKS_VQ28 PSWRQ2: blk_cnt_per_vq29 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_29 PSWRQ2_REG_MAX_BLKS_VQ29 PSWRQ2: blk_cnt_per_vq30 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_30 PSWRQ2_REG_MAX_BLKS_VQ30 PSWRQ2: L2P close the gate is asserted PSWRQ2_REG_L2P_CLOSE_GATE_STS PSWRQ2: MISC close the gate is asserted PSWRQ2_REG_MISC_CLOSE_GATE_STS PSWRQ2: MISC stall mem is asserted PSWRQ2_REG_MISC_STALL_MEM_STS PSWRQ: Interrupt status is not 0 PSWRQ_REG_INT_STS PSWWR: Interrupt status is not 0 PSWWR_REG_INT_STS PSWWR: Details of first request that triggered any of the 3 EOP interrupts: [4:0] - client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. [10:8] - number_of_valid_64bit_words[2:0] or number_of_valid_128bit_words[1:0] according to the definition in the spec. [13:11] - The type of interrupt the logging corresponds to: [11] - pglue_eop_error; [12] - pglue_lsr_error; [13] - pglue_eop_error_in_line. [14] - valid - indicates if there was a request that triggered EOP interrupt since this register was cleared. PSWWR2_REG_PGLUE_EOP_ERR_DETAILS PSWWR: PRM payload FIFO is not empty. PSWWR2_REG_PRM_CURR_FILL_LEVEL PSWWR: CDU payload FIFO is not empty. PSWWR2_REG_CDU_CURR_FILL_LEVEL PSWWR2: Interrupt status is not 0 PSWWR2_REG_INT_STS PSWWR2: Parity status 0 is not 0 PSWWR2_REG_PRTY_STS_H_0 PSWWR2: Parity status 1 is not 0 PSWWR2_REG_PRTY_STS_H_1 PSWWR2: Parity status 2 is not 0 PSWWR2_REG_PRTY_STS_H_2 PSWWR2: Parity status 3 is not 0 PSWWR2_REG_PRTY_STS_H_3 PSWRD: Full is asserted from at least one client. PSWRD_REG_FIFO_FULL_STATUS PSWRD: Interrupt status is not 0 PSWRD_REG_INT_STS PSWRD2: rd_start_init is not 1 PSWRD2 Block is not initialized PSWRD2_REG_START_INIT PSWRD2: rd_init_done is not 1 PSWRD2: Block is not initialized PSWRD2_REG_INIT_DONE PSWRD2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - Sub Request length minus 1. (29) - first SR. (30) - last SR. PSWRD2_REG_CPL_ERR_DETAILS PSWRD2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (9:5) - client ID. (10) - valid bit. PSWRD2_REG_CPL_ERR_DETAILS2 PSWRD2: P0 All delivery ports are not idle PSWRD2_REG_PORT_IS_IDLE_0 PSWRD2: P1 All delivery ports are not idle PSWRD2_REG_PORT_IS_IDLE_1 PSWRD2: rd_almost_full is not 0 PSWRD2_REG_ALMOST_FULL_0 PSWRD2: Interrupt status is not 0 PSWRD2_REG_INT_STS PSWRD2: Parity status 0 is not 0 PSWRD2_REG_PRTY_STS_H_0 PSWRD2: Parity status 1 is not 0 PSWRD2_REG_PRTY_STS_H_1 PSWRD2: PSWRD inputs are disabled PSWRD2_REG_DISABLE_INPUTS PSWHST2: HST header FIFO status is not 0 PSWHST2_REG_HEADER_FIFO_STATUS PSWHST2: HST data FIFO status is not 0 PSWHST2_REG_DATA_FIFO_STATUS PSWHST2: Interrupt status is not 0 PSWHST2_REG_INT_STS PSWHST: HST Close the gates: Discarding internal writes PSWHST_REG_DISCARD_INTERNAL_WRITES_STATUS PSWHST: HST Close the gates: Discarding doorbells PSWHST_REG_DISCARD_DOORBELLS_STATUS PSWHST: HST arbiter is not idle PSWHST_REG_ARB_IS_IDLE PSWHST: Incorrect transaction took place PSWHST_REG_INCORRECT_ACCESS_VALID PSWHST_REG_INCORRECT_ACCESS_DATA PSWHST_REG_INCORRECT_ACCESS_LENGTH PSWHST_REG_INCORRECT_ACCESS_ADDRESS PSWHST: Zone A permission violation occurred PSWHST_REG_PER_VIOLATION_VALID PSWHST_REG_PER_VIOLATION_DATA PSWHST: HST: not all credits available from internal write sources. (1:0) usdm; (3:2) xsdm; (5:4) msdm; (7:6) ysdm; (9:8) psdm; (11:10) tsdm; (13:12) pbf; (16:14) qm; (18:17) nig PSWHST_REG_SOURCE_CREDITS_AVAIL PSWHST: HST: Internal write source client consumed more credits than it is allowed. 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 TSDM; 7 PBF; 8 QM; 9 NIG. PSWHST_REG_SOURCE_CREDIT_VIOL_VALID PSWHST_REG_SOURCE_CREDIT_VIOL_DATA PSWHST: HST: not all credits available to internal write destinations. (1:0) usdm; (3:2) xsdm; (5:4) msdm; (7:6) ysdm; (9:8) psdm; (11:10) tsdm; (13:12) igu; (15:14) cau PSWHST_REG_DEST_CREDITS_AVAIL PSWHST: HST: Is in drain mode (after target timeout). PSWHST_REG_IS_IN_DRAIN_MODE PSWHST: HST: Target Timeout address. PSWHST_REG_TIMEOUT_VALID PSWHST_REG_TIMEOUT_ADDRESS PSWHST: HST: Target Timeout details. (29:24) - length in DWs; (23:16) - byte enable; (15:13) - pfid; (12:6) - vfid; (5) - vf_valid; (4:1) - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); (0) - 0 - read 1 - write. PSWHST_REG_TIMEOUT_VALID PSWHST_REG_TIMEOUT_DATA PSWHST: Each entry contains a bit mask for PSWHST source arbiter clients. '1' means this client is waiting for the arbiter. Each entry refers to a different source arbiter. Entry decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 IGU; 7 CAU). Bit mask decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG; 9 HOST WR; 10 HOST RD) PSWHST_REG_CLIENTS_WAITING_TO_SOURCE_ARB PSWHST: Interrupt status is not 0 PSWHST_REG_INT_STS PSWHST: Parity status is not 0 PSWHST_REG_PRTY_STS_H_0 PGLUE_B: Interrupt status & 0x76417C is not 0 PGLUE_B_REG_INT_STS PGLUE_B: Interrupt status & 0x01BC01 is not 0 PGLUE_B_REG_INT_STS PGLUE_B: Parity status is not 0 PGLUE_B_REG_PRTY_STS_H_0 PGLUE_B: pgl_write_blocked is not 0 PGLUE_B: PCI was closed for write requests while a request arrived (might happen in DrvSim due to Timers) PGLUE_B_REG_PGL_WRITE_BLOCKED PGLUE_B: pgl_read_blocked is not 0 PGLUE_B: PCI was closed for read requests while a request arrived (might happen in DrvSim due to Timers) PGLUE_B_REG_PGL_READ_BLOCKED PGL TX Read FIFO is not empty. PGLUE_B_REG_READ_FIFO_OCCUPANCY_LEVEL Bit 0 - Target memory read with a correctable error. Bit 1 - Target memory read with an uncorrectable error. Bit 2 - Configuration RW with a correctable error. Bit 3 - Configuration RW with an uncorrectable error. Bit 4 - Target memory write or MSGD with a correctable error. Bit 5 - Target memory write or MSGD with an uncorrectable error. Bit 6 - Master completion with a correctable error. Bit 7 - Master completion with an uncorrectable error. PGLUE_B_REG_RX_LEGACY_ERRORS PGLUE_B: There is data which is ready PGLUE_B_REG_PGL_TXW_CDTS PGL: Cfg-Space A request is set PGLUE_B_REG_CFG_SPACE_A_REQUEST PGL: Cfg-Space B request is set PGLUE_B_REG_CFG_SPACE_B_REQUEST PGL: FLR request is set for VF addresses 31-0 PGLUE_B_REG_FLR_REQUEST_VF_31_0 PGL: FLR request is set for VF addresses 63-32 PGLUE_B_REG_FLR_REQUEST_VF_63_32 PGL: FLR request is set for VF addresses 95-64 PGLUE_B_REG_FLR_REQUEST_VF_95_64 PGL: FLR request is set for VF addresses 127-96 PGLUE_B_REG_FLR_REQUEST_VF_127_96 PGL: FLR request is set for VF addresses 159-128 PGLUE_B_REG_FLR_REQUEST_VF_159_128 PGL: FLR request is set for VF addresses 191-160 PGLUE_B_REG_FLR_REQUEST_VF_191_160 PGL: FLR request is set for PF addresses 7-0 PGLUE_B_REG_FLR_REQUEST_PF_31_0 PGL: SR-IOV disable request is set PGLUE_B_REG_SR_IOV_DISABLED_REQUEST PGLUE_B: was_error for VFs 0-31 is not 0 PGLUE_B_REG_WAS_ERROR_VF_31_0 PGLUE_B: was_error for VFs 32-63 is not 0 PGLUE_B_REG_WAS_ERROR_VF_63_32 PGLUE_B: was_error for VFs 64-95 is not 0 PGLUE_B_REG_WAS_ERROR_VF_95_64 PGLUE_B: was_error for VFs 96-127 is not 0 PGLUE_B_REG_WAS_ERROR_VF_127_96 PGLUE_B: was_error for VFs 128-159 is not 0 PGLUE_B_REG_WAS_ERROR_VF_159_128 PGLUE_B: was_error for VFs 160-191 is not 0 PGLUE_B_REG_WAS_ERROR_VF_191_160 PGLUE_B: was_error for PFs 0-15 is not 0 PGLUE_B_REG_WAS_ERROR_PF_31_0 PGLUE_B: Completion received with error. (3:0) - PFID. (4) - VF_VALID. (12:5) - VFID. (14:13) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (15) - valid bit. PGLUE_B_REG_RX_ERR_DETAILS PGLUE_B: ATS TCPL received with error. (3:0) - PFID. (4) - VF_VALID. (12:5) - VFID. (14:13) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (19:15) - OTB Entry ID. (20) - valid bit. PGLUE_B_REG_RX_TCPL_ERR_DETAILS PGLUE_B: Error in master write. Address(31:0) is not 0 PGLUE_B_REG_TX_ERR_WR_ADD_31_0 PGLUE_B: Error in master write. Address(63:32) is not 0 PGLUE_B_REG_TX_ERR_WR_ADD_63_32 PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (17:5) - Length in bytes. (19) - VF_VALID. (23:20) - PFID. (31:24) - VFID. PGLUE_B_REG_TX_ERR_WR_DETAILS PGLUE_B: Error in master write. Error details 2nd register is not 0. (15:0) Request ID. (20:16) client ID. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request. (25) - last SR. (26) - valid bit. PGLUE_B_REG_TX_ERR_WR_DETAILS2 PGLUE: Error in master read address(31:0) is not 0 PGLUE_B_REG_TX_ERR_RD_ADD_31_0 PGLUE_B: Error in master read address(63:32) is not 0 PGLUE_B_REG_TX_ERR_RD_ADD_63_32 PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (5) Is TREQ. (18:6) - Length in bytes. (19) - VF_VALID. (23:20) - PFID. (31:24) - VFID. PGLUE_B_REG_TX_ERR_RD_DETAILS PGLUE_B: Error in master read Error details 2nd register is not 0. (15:0) Request ID. (20:16) client ID. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request. (25) last SR. (26) valid bit. PGLUE_B_REG_TX_ERR_RD_DETAILS2 PGLUE_B: Target VF length violation access. (12:0) Address in DWs (bits (14:2) of byte address). (14:13) BAR. (22:15) VFID. (26:23) - PFID. PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS PGLUE_B: Target VF length violation access. (5:0) - Length in DWs. (6) valid bit. PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS2 PGLUE_B: Target VF GRC space access failed permission check. (14:0) Address. (15) w_nr: 0 - Read; 1 - Write. (23:16) VFID. (27:24) - PFID. (28) - valid bit. PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS PGLUE: Address(31:0) of first master read request with length equals to 0. PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 PGLUE: Address(63:32) of first master read request with length equals to 0. PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 Details of first read request with length = 0. (4:0) VQID. (5) Is TREQ. (9:6) - PFID. (10) - VF_VALID. (18:11) - VFID. (23:19) client ID. (24) - last SR. (25) valid. PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS Details of first target Read Write access to the admin window that have a length bigger than 1DW or first byte enable != 0xf . (9:0) Address in DWs (bits (11:2) of byte address). (13:10) BE first. (17:14) BE last. (21:18) - PFID. (27:22) - Length in DWs. (28) valid bit. PGLUE_B_REG_ADMIN_WINDOW_VIOLATION_DETAILS Details of first target Read/Write access where pretend register contains an out of range function. (3:0) - original PFID. (7:4) Pretend PFID. (15:8) Pretend VFID. (16) Pretend vf_valid. (20:17) Pretend register: 0-11 - One of the PF windows pretend. 12 - global pretend register. (21) valid bit. PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_DETAILS Address of first target Read Write access where pretend register contains an out of range function. PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_ADDRESS PGL TX Write FIFO is not empty. PGLUE_B_REG_WRITE_FIFO_OCCUPANCY_LEVEL PGLUE_B: Illegal address in master flow. Address(31:0). PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_31_0 PGLUE_B: Illegal address in master flow. Address(63:32). PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_63_32 PGLUE_B: Illegal address in master flow. (4:0) VQID. (5) - first SR. (18:6) - Length in bytes. (19) - VF_VALID. (23:20) - PFID. (31:24) - VFID. PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS PGLUE_B: Illegal address in master flow. (15:0) Request ID. (20:16) client ID. (21) Illegal address cause: 0 - address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. (22) - write_n_read: 0 - read; 1 - write. (23) last SR. (24) valid bit. PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS2 PGLUE_B: There are outstanding read requests for tags 0-31. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_31_0 PGLUE_B: There are outstanding read requests for tags 32-63. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_63_32 PGLUE_B: There are outstanding read requests for tags 64-95. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_95_64 PGLUE_B: There are outstanding read requests for tags 96-127. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_127_96 PGLUE_B: Transaction with VF ILT error was dropped. Logical address(31:0). PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 PGLUE_B: Transaction with VF ILT error was dropped. Logical address(63:32). PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 PGLUE_B: Transaction with VF ILT error was dropped. (4:0) VQID. (5) - first SR. (18:6) - Length in bytes. (19) - VF_VALID. (23:20) - PFID. (31:24) - VFID. PGLUE_B_REG_VF_ILT_ERR_DETAILS PGLUE_B: Transaction with VF ILT error was dropped. (15:0) Request ID. (20:16) client ID. (21) write_n_read: 0 - read; 1 - write. (22) last SR. (23) valid bit. PGLUE_B_REG_VF_ILT_ERR_DETAILS2 TM: TM_REG_INT_STS_0 bits 30:23 are set, one of the errored commands attentions is asserted TM: There is an interrupt on bits 23-30 of register 0 TM_REG_INT_STS_0 TM: TM_REG_INT_STS_0 bit 31 is set, cload_res_loaderr_conn attention is asserted TM: A load response with error return from the CCFC TM_REG_INT_STS_0 TM: TM_REG_INT_STS_0 bits 22:0 are set, one of the FIFOs overflow or underrun attentions is asserted (bit 0 - address error) TM: There is an interrupt on bits 0-22 of register 0 TM_REG_INT_STS_0 TM: TM_REG_INT_STS_1 bits 10,4:1 are set, one of cload_res_validerr_task, pxp_rd_data_eop_bvalid, context_wr_last, context_rd_last, cload_res_validerr_conn attentions is asserted TM: There is an interrupt on bits of register 1 TM_REG_INT_STS_1 TM: Parity status is not 0 TM_REG_PRTY_STS_H_0 TM: PXP_READ_DATA_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in PXP->TM data interface TM_REG_PXP_READ_DATA_FIFO_STATUS TM: PXP_READ_CTRL_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in TM->PXP control data interface TM_REG_PXP_READ_CTRL_FIFO_STATUS TM: CFC_LOAD_ECHO_FIFO_STATUS is not 0, FIFO is not empty TM: load requests from the CCFC did not return TM_REG_CFC_LOAD_ECHO_FIFO_STATUS TM: TM_REG_CLIENT_OUT_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending expirations waiting to be sent to clients TM_REG_CLIENT_OUT_FIFO_STATUS TM: TM_REG_CLIENT_IN_PBF_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in PBF->TM interface TM_REG_CLIENT_IN_PBF_FIFO_STATUS TM: TM_REG_CLIENT_IN_XCM_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in XCM->TM interface TM_REG_CLIENT_IN_XCM_FIFO_STATUS TM: TM_REG_CLIENT_IN_TCM_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in TCM->TM interface TM_REG_CLIENT_IN_TCM_FIFO_STATUS TM: TM_REG_CLIENT_IN_UCM_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending messages in UCM->TM interface TM_REG_CLIENT_IN_UCM_FIFO_STATUS TM: TM_REG_EXPIRATION_CMD_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending expirations waiting internally in Timers TM_REG_EXPIRATION_CMD_FIFO_STATUS TM: TM_REG_AC_COMMAND_FIFO_STATUS is not 0, FIFO is not empty TM: There are pending AC return requests pending TM_REG_AC_COMMAND_FIFO_STATUS TCFC: ll_init_done is not 1 TCFC: LL is not initialized TCFC_REG_LL_INIT_DONE TCFC: ac_init_done is not 1 TCFC: AC is not initialized TCFC_REG_AC_INIT_DONE TCFC: cam_init_done is not 1 TCFC: CAM is not initialized TCFC_REG_CAM_INIT_DONE TCFC: tidram_init_done is not 1 TCFC: TIDRAM is not initialized TCFC_REG_TIDRAM_INIT_DONE TCFC: Interrupt is set TCFC Error TCFC_REG_INT_STS_0 TCFC_REG_ERROR_VECTOR TCFC_REG_ERROR_DATA1 TCFC_REG_ERROR_DATA2 TCFC_REG_ERROR_DATA3 TCFC_REG_ERROR_DATA4 TCFC: Parity status is not 0 TCFC_REG_PRTY_STS_H_0 TCFC: There are LCIDs in ARRIVING state TCFC_REG_LSTATE_ARRIVING TCFC: There are LCIDs in LEAVING state TCFC_REG_LSTATE_LEAVING TCFC: CDU load credits number is different than reset value TCFC_REG_CDULD_CREDIT TCFC: CDU write back credits number is different than reset value TCFC_REG_CDUWB_CREDIT CCFC: ll_init_done is not 1 CCFC: LL is not initialized CCFC_REG_LL_INIT_DONE CCFC: ac_init_done is not 1 CCFC: AC is not initialized CCFC_REG_AC_INIT_DONE CCFC: cam_init_done is not 1 CCFC: CAM is not initialized CCFC_REG_CAM_INIT_DONE CCFC: tidram_init_done is not 1 CCFC: TIDRAM is not initialized CCFC_REG_TIDRAM_INIT_DONE CCFC: Interrupt is set CCFC Error CCFC_REG_INT_STS_0 CCFC_REG_ERROR_VECTOR CCFC_REG_ERROR_DATA1 CCFC_REG_ERROR_DATA2 CCFC_REG_ERROR_DATA3 CCFC_REG_ERROR_DATA4 CCFC: Parity status is not 0 CCFC_REG_PRTY_STS_H_0 CCFC: CAM Parity status is not 0 CCFC_REG_PRTY_STS CCFC: There are LCIDs in ARRIVING state CCFC_REG_LSTATE_ARRIVING CCFC: There are LCIDs in LEAVING state CCFC_REG_LSTATE_LEAVING CCFC: CDU load credits number is different than reset value CCFC_REG_CDULD_CREDIT CCFC: CDU write back credits number is different than reset value CCFC_REG_CDUWB_CREDIT QM: Interrupt status is not 0 QM: There is an interrupt on register 0 QM_REG_INT_STS QM: Parity status for specific mems is not 0 QM_REG_PRTY_STS QM: Parity status 0 is not 0 QM_REG_PRTY_STS_H_0 QM: Parity status 1 is not 0 QM_REG_PRTY_STS_H_1 QM: Parity status 2 is not 0 QM_REG_PRTY_STS_H_2 QM: wrc_fifolvl is not 0 (see qm_rf for cm idx enumeration) QM: There are pending messages in the input FIFOs QM_REG_WRC_FIFOLVL_0 QM: CCFC load request buffer credit for TX PQ-s is not equal to the initial credit QM: CCFC credit on tx queues interface is not equal to init val QM_REG_OUTLDREQCRDCONNTX QM_REG_OUTLDREQSIZECONNTX QM: CCFC/TCFC load request buffer credit for Other PQ-s is not equal to the initial credit QM: CCFC/TCFC credit on other queues interface is not equal to init val QM_REG_OUTLDREQCRDCONNOTHER QM_REG_OUTLDREQSIZECONNOTHER QM: OVFQNUMTX is not 0 QM_REG_OVFQNUMTX QM: OVFERRORTX is not 0 QM: There is an overflow error on one of the tx queues QM_REG_OVFERRORTX QM_REG_OVFQNUMTX QM: OVFQNUMOTHER is not 0 QM: An o queues QM_REG_OVFQNUMOTHER QM: OVFERROROTHER is not 0 QM: There is an overflow error on one of the other queues QM_REG_OVFERROROTHER QM_REG_OVFQNUMOTHER QM: CM credit on the pop interface #0 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on MCM sec pop interface is not equal to init val QM_REG_CMCRD_0 QM_REG_CMINITCRD_0 QM: CM credit on the pop interface #1 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on MCM pri pop interface is not equal to init val QM_REG_CMCRD_1 QM_REG_CMINITCRD_1 QM: CM credit on the pop interface #2 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on UCM sec pop interface is not equal to init val QM_REG_CMCRD_2 QM_REG_CMINITCRD_2 QM: CM credit on the pop interface #3 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on UCM pri pop interface is not equal to init val QM_REG_CMCRD_3 QM_REG_CMINITCRD_3 QM: CM credit on the pop interface #4 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on TCM sec pop interface is not equal to init val QM_REG_CMCRD_4 QM_REG_CMINITCRD_4 QM: CM credit on the pop interface #5 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on TCM pri pop interface is not equal to init val QM_REG_CMCRD_5 QM_REG_CMINITCRD_5 QM: CM credit on the pop interface #6 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on YCM sec pop interface is not equal to init val QM_REG_CMCRD_6 QM_REG_CMINITCRD_6 QM: CM credit on the pop interface #7 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on YCM pri pop interface is not equal to init val QM_REG_CMCRD_7 QM_REG_CMINITCRD_7 QM: CM credit on the pop interface #8 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on XCM sec pop interface is not equal to init val QM_REG_CMCRD_8 QM_REG_CMINITCRD_8 QM: CM credit on the pop interface #9 is not equal to init val (see qm_rf for cm idx enumeration) QM: CM credit on XCM pri pop interface is not equal to init val QM_REG_CMCRD_9 QM_REG_CMINITCRD_9 RDIF: interrupt status 0 is not 0 RDIF: There is an interrupt on register 0 RDIF_REG_INT_STS TDIF: interrupt status 0 is not 0 TDIF: There is an interrupt on register 0 TDIF_REG_INT_STS TDIF: Parity status is not 0 TDIF_REG_PRTY_STS_H_0 BRB: Interrupt status 0 is set BRB: Fatal BRB error BRB_REG_INT_STS_0 BRB_REG_STOPPED_RD_REQ BRB_REG_STOPPED_RLS_REQ BRB: Interrupt status 1 is set BRB: Fatal BRB error BRB_REG_INT_STS_1 BRB: Interrupt status 2 is set BRB: Fatal BRB error BRB_REG_INT_STS_2 BRB: Interrupt status 3 is set BRB: Fatal BRB error BRB_REG_INT_STS_3 BRB: Interrupt status 4 is set to values differ from 0x20_0000 BRB: Fatal BRB error BRB_REG_INT_STS_4 BRB_REG_STOPPED_RD_REQ BRB_REG_STOPPED_RLS_REQ BRB: Parity status 0 is not 0 BRB_REG_PRTY_STS_H_0 BRB: Parity status 1 is not 0 BRB_REG_PRTY_STS_H_1 BRB: Write client bandwidth full IF is not 0 BRB: Global full to write clients is asserted (should be temporary due to big RAM BW limitations) BRB_REG_WC_BANDWIDTH_IF_FULL BRB: Read packet client IF full is not 0 BRB: One of the read clients asserted full to BRB BRB_REG_RC_PKT_IF_FULL BRB: Read packet client FIFOs are not empty BRB: Read packet client 0 FIFOs are not empty BRB_REG_RC_PKT_EMPTY_0 BRB: Read SOP client FIFOs are not empty BRB: Read SOP client FIFOs are not empty BRB_REG_RC_SOP_EMPTY BRB: Link list arbiter is not empty BRB: Link list arbiter is not empty BRB_REG_LL_ARB_EMPTY BRB: Stop packet counter status is not 0 BRB: The number of packets in the pipeline (from EOP read request to release) BRB_REG_STOP_PACKET_COUNTER BRB: Stop byte counter status is not 0 BRB: The number of bytes in the pipeline (from EOP read request to release) BRB_REG_STOP_BYTE_COUNTER BRB: Read packet client state machines are not idle BRB: Read packet client state machines are not idle BRB_REG_RC_PKT_STATE TC 0 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 0 BRB_REG_MAC0_TC_OCCUPANCY_0 TC 1 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 1 BRB_REG_MAC0_TC_OCCUPANCY_1 TC 2 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 2 BRB_REG_MAC0_TC_OCCUPANCY_2 TC 3 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 3 BRB_REG_MAC0_TC_OCCUPANCY_3 TC 4 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 4 BRB_REG_MAC0_TC_OCCUPANCY_4 TC 5 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 5 BRB_REG_MAC0_TC_OCCUPANCY_5 TC 6 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 6 BRB_REG_MAC0_TC_OCCUPANCY_6 TC 7 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 7 BRB_REG_MAC0_TC_OCCUPANCY_7 TC 8 in MAC 0 occupancy is not 0x0 There are packets in BRB belonging to MAC 0 traffic-class 8 BRB_REG_MAC0_TC_OCCUPANCY_8 TC 0 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 0 BRB_REG_MAC1_TC_OCCUPANCY_0 TC 1 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 1 BRB_REG_MAC1_TC_OCCUPANCY_1 TC 2 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 2 BRB_REG_MAC1_TC_OCCUPANCY_2 TC 3 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 3 BRB_REG_MAC1_TC_OCCUPANCY_3 TC 4 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 4 BRB_REG_MAC1_TC_OCCUPANCY_4 TC 5 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 5 BRB_REG_MAC1_TC_OCCUPANCY_5 TC 6 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 6 BRB_REG_MAC1_TC_OCCUPANCY_6 TC 7 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 7 BRB_REG_MAC1_TC_OCCUPANCY_7 TC 8 in MAC 1 occupancy is not 0x0 There are packets in BRB belonging to MAC 1 traffic-class 8 BRB_REG_MAC1_TC_OCCUPANCY_8 XYLD : Pending Message counter to External event1 is not 0 XYLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR XYLD : Pending Message counter to External event2 is not 0 XYLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR XYLD : Pending Message counter to External event3 is not 0 XYLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR XYLD : Pending Message counter to External event4 is not 0 XYLD: There are outstanding messages waiting for 'done' indication from XSDM XYLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR XYLD : Pending Message counter to External event5 is not 0 XYLD: There are outstanding messages waiting for 'done' indication from XCM XYLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR XYLD: XYLD_REG_FOC_REMAIN_CREDITS is not XYLD_REG_FOCI_FOC_CREDITS XYLD: YCM didn't ACK all the message cycles sent by XYLD XYLD_REG_FOC_REMAIN_CREDITS XYLD_REG_FOCI_FOC_CREDITS XYLD : Pending Message counter is not 0 XYLD:There are outstanding PCI read requests XYLD_REG_PCI_PENDING_MSG_CTR XYLD : CCFC REQ Pending Message counter is not 0 XYLD:There are outstanding CCFC load requests XYLD_REG_DBG_PENDING_CCFC_REQ XYLD : TCFC REQ Pending Message counter is not 0 XYLD:There are outstanding TCFC load requests XYLD_REG_DBG_PENDING_TCFC_REQ TMLD : Pending Message counter to External event1 is not 0 TMLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR TMLD : Pending Message counter to External event2 is not 0 TMLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR TMLD : Pending Message counter to External event3 is not 0 TMLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR TMLD : Pending Message counter to External event4 is not 0 TMLD: There are outstanding messages waiting for 'done' indication from TSDM TMLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR TMLD : Pending Message counter to External event5 is not 0 TMLD: There are outstanding messages waiting for 'done' indication from TCM TMLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR TMLD: TMLD_REG_FOC_REMAIN_CREDITS is not TMLD_REG_FOCI_FOC_CREDITS TMLD: MCM didn't ACK all the message cycles sent by TMLD TMLD_REG_FOC_REMAIN_CREDITS TMLD_REG_FOCI_FOC_CREDITS TMLD : CCFC REQ Pending Message counter is not 0 TMLD:There are outstanding CCFC load requests TMLD_REG_DBG_PENDING_CCFC_REQ TMLD : TCFC REQ Pending Message counter is not 0 TMLD:There are outstanding TCFC load requests TMLD_REG_DBG_PENDING_TCFC_REQ MULD : Pending Message counter to External event1 is not 0 MULD: There are outstanding messages waiting for short 'done' indication from PRM MULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR MULD : Pending Message counter to External event2 is not 0 MULD: There are outstanding messages waiting for long 'done' indication from PRM MULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR MULD : Pending Message counter to External event3 is not 0 MULD: There are outstanding messages waiting for 'done' indication from MCM MULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR MULD : Pending Message counter to External event4 is not 0 MULD: There are outstanding messages waiting for 'done' indication from YCM MULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR MULD : Pending Message counter to External event5 is not 0 MULD: There are outstanding messages waiting for 'done' indication from XCM MULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR MULD: MULD_REG_FOC_REMAIN_CREDITS is not MULD_REG_FOCI_FOC_CREDITS MULD: UCM didn't ACK all the message cycles sent by MULD MULD_REG_FOC_REMAIN_CREDITS MULD_REG_FOCI_FOC_CREDITS MULD: BD Pending Message counter is not 0 MULD:There are outstanding BD fetch requests MULD_REG_BD_PENDING_MSG_CTR MULD: SGE Pending Message counter is not 0 MULD:There are outstanding SGE fetch requests MULD_REG_SGE_PENDING_MSG_CTR MULD : Pending Message counter is not 0 MULD:There are outstanding PCI read requests MULD_REG_PCI_PENDING_MSG_CTR MULD : CCFC REQ Pending Message counter is not 0 MULD:There are outstanding CCFC load requests MULD_REG_DBG_PENDING_CCFC_REQ MULD : TCFC REQ Pending Message counter is not 0 MULD:There are outstanding TCFC load requests MULD_REG_DBG_PENDING_TCFC_REQ NIG: Error in FIFOs or accessed address. NIG: Fatal NIG error NIG_REG_INT_STS_0 NIG: Error in SOPQs. NIG: Fatal NIG error NIG_REG_INT_STS_1 NIG: Error in FIFOs accesses for port 0. NIG: Fatal NIG error NIG_REG_INT_STS_2 NIG: Pause too long interrupt occurred in port 0. NIG: PAUSE / PFC was asserted for more than a pre-defined time on port #0 NIG_REG_INT_STS_3 NIG_REG_FLOWCTRL_MODE NIG_REG_RX_FLOWCTRL_STATUS NIG: Error in FIFOs accesses for port 1. NIG: Fatal NIG error NIG_REG_INT_STS_4 NIG: Pause too long interrupt occurred in port 1. NIG: PAUSE / PFC was asserted for more than a pre-defined time on port #1 NIG_REG_INT_STS_5 NIG_REG_FLOWCTRL_MODE NIG_REG_RX_FLOWCTRL_STATUS NIG: Parity status 0 is not 0 NIG_REG_PRTY_STS_H_0 NIG: Parity status 1 is not 0 NIG_REG_PRTY_STS_H_1 NIG: Parity status 2 is not 0 NIG_REG_PRTY_STS_H_2 NIG: Parity status 3 is not 0 NIG_REG_PRTY_STS_H_3 NIG: LB SOPQs are not empty NIG: LB SOP descriptor queues are not empty NIG_REG_LB_SOPQ_EMPTY NIG: TX SOPQs are not empty NIG: TX SOP descriptor queues are not empty NIG_REG_TX_SOPQ_EMPTY NIG: TX MAC FIFO for the port is not empty NIG: TX FIFO for transmitting data to MAC is not empty NIG_REG_TX_MACFIFO_EMPTY NIG: RX LLH RFIFO for the port is not empty NIG: RX LLH result FIFO is not empty NIG_REG_RX_LLH_RFIFO_EMPTY NIG: Error in BTB FIFO for LB path for the port . NIG: LB BTB FIFO is not empty NIG_REG_LB_BTB_FIFO_EMPTY NIG: LB LLH RFIFO for the port is not empty NIG: LB LLH result FIFO is not empty NIG_REG_LB_LLH_RFIFO_EMPTY NIG: TS MSB in the MAC is out of sync. NIG: PTP TS value error NIG_REG_RX_PTP_TS_MSB_ERR NIG_REG_RX_PTP_EN NIG: Error in BTB FIFO for TX path for the port . NIG: TX BTB FIFO is not empty NIG_REG_TX_BTB_FIFO_EMPTY NIG: Debug FIFO is not empty NIG: Debug traffic FIFO is not empty NIG_REG_DEBUG_FIFO_EMPTY PTU: PXP ERROR CTR is not 0 PTU: There were errors returned from the PXP PTU_REG_PXP_ERR_CTR PTU: INV ERROR CTR is not 0 PTU: There were translation requests during invalidation PTU_REG_INV_ERR_CTR PTU: PBF FILL is not 0 PTU: There are pending messages in PBF->PTU interface PTU_REG_PBF_FILL_LEVEL PTU: PRM FILL is not 0 PTU: There are pending messages in PRM->PTU interface PTU_REG_PRM_FILL_LEVEL PTU: INT STS Register is not 0 PTU: There is an interrupt on register 0 PTU_REG_INT_STS PTU: Parity status is not 0 PTU_REG_PRTY_STS_H_0 CDU: Interrupt Status is not 0 CDU Error CDU_REG_INT_STS CDU_REG_CCFC_CVLD_ERROR_DATA CDU_REG_TCFC_CVLD_ERROR_DATA CDU_REG_CCFC_LD_L1_NUM_ERROR_DATA CDU_REG_TCFC_LD_L1_NUM_ERROR_DATA CDU_REG_CCFC_WB_L1_NUM_ERROR_DATA CDU_REG_TCFC_WB_L1_NUM_ERROR_DATA CDU: Parity status is not 0 CDU_REG_PRTY_STS_H_0 PBF: Parity status 0 is not 0 PBF_REG_PRTY_STS_H_0 PBF: Parity status 1 is not 0 PBF_REG_PRTY_STS_H_1 PBF: Data was received with 'error' indication from PXP/TDIF PBF: Data was received with error indication from PXP/TDIF PBF_REG_NUM_PKTS_RECEIVED_WITH_ERROR PBF: Packet/s were sent to BTB with 'error' indication PBF: Packet/s were sent to BTB with 'error' indication PBF_REG_NUM_PKTS_SENT_WITH_ERROR_TO_BTB PBF: Packet/s were sent to BTB with 'drop' indication PBF: Packet/s were sent to BTB with 'drop' indication PBF_REG_NUM_PKTS_SENT_WITH_DROP_TO_BTB PBF: Y command queue of VOQ0 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #0 PBF_REG_YCMD_QS_CMD_CNT_VOQ0 PBF: Y command queue of VOQ0 is not empty PBF: There are outstanding command in the command queue of traffic-class #0 PBF_REG_YCMD_QS_OCCUPANCY_VOQ0 PBF: There are allocated blocks in BTB for VOQ0 PBF: There are packets in BTB belonging to traffic-class #0 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ0 PBF: Y command queue of VOQ1 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #1 PBF_REG_YCMD_QS_CMD_CNT_VOQ1 PBF: Y command queue of VOQ1 is not empty PBF: There are outstanding command in the command queue of traffic-class #1 PBF_REG_YCMD_QS_OCCUPANCY_VOQ1 PBF: There are allocated blocks in BTB for VOQ1 PBF: There are packets in BTB belonging to traffic-class #1 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ1 PBF: Y command queue of VOQ2 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #2 PBF_REG_YCMD_QS_CMD_CNT_VOQ2 PBF: Y command queue of VOQ2 is not empty PBF: There are outstanding command in the command queue of traffic-class #2 PBF_REG_YCMD_QS_OCCUPANCY_VOQ2 PBF: There are allocated blocks in BTB for VOQ2 PBF: There are packets in BTB belonging to traffic-class #2 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ2 PBF: Y command queue of VOQ3 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #3 PBF_REG_YCMD_QS_CMD_CNT_VOQ3 PBF: Y command queue of VOQ3 is not empty PBF: There are outstanding command in the command queue of traffic-class #3 PBF_REG_YCMD_QS_OCCUPANCY_VOQ3 PBF: There are allocated blocks in BTB for VOQ3 PBF: There are packets in BTB belonging to traffic-class #3 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ3 PBF: Y command queue of VOQ4 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #4 PBF_REG_YCMD_QS_CMD_CNT_VOQ4 PBF: Y command queue of VOQ4 is not empty PBF: There are outstanding command in the command queue of traffic-class #4 PBF_REG_YCMD_QS_OCCUPANCY_VOQ4 PBF: There are allocated blocks in BTB for VOQ4 PBF: There are packets in BTB belonging to traffic-class #4 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ4 PBF: Y command queue of VOQ5 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #5 PBF_REG_YCMD_QS_CMD_CNT_VOQ5 PBF: Y command queue of VOQ5 is not empty PBF: There are outstanding command in the command queue of traffic-class #5 PBF_REG_YCMD_QS_OCCUPANCY_VOQ5 PBF: There are allocated blocks in BTB for VOQ5 PBF: There are packets in BTB belonging to traffic-class #5 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ5 PBF: Y command queue of VOQ6 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #6 PBF_REG_YCMD_QS_CMD_CNT_VOQ6 PBF: Y command queue of VOQ6 is not empty PBF: There are outstanding command in the command queue of traffic-class #6 PBF_REG_YCMD_QS_OCCUPANCY_VOQ6 PBF: There are allocated blocks in BTB for VOQ6 PBF: There are packets in BTB belonging to traffic-class #6 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ6 PBF: Y command queue of VOQ7 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #7 PBF_REG_YCMD_QS_CMD_CNT_VOQ7 PBF: Y command queue of VOQ7 is not empty PBF: There are outstanding command in the command queue of traffic-class #7 PBF_REG_YCMD_QS_OCCUPANCY_VOQ7 PBF: There are allocated blocks in BTB for VOQ7 PBF: There are packets in BTB belonging to traffic-class #7 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ7 PBF: Y command queue of VOQ8 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #8 PBF_REG_YCMD_QS_CMD_CNT_VOQ8 PBF: Y command queue of VOQ8 is not empty PBF: There are outstanding command in the command queue of traffic-class #8 PBF_REG_YCMD_QS_OCCUPANCY_VOQ8 PBF: There are allocated blocks in BTB for VOQ8 PBF: There are packets in BTB belonging to traffic-class #8 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ8 PBF: Y command queue of VOQ9 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #9 PBF_REG_YCMD_QS_CMD_CNT_VOQ9 PBF: Y command queue of VOQ9 is not empty PBF: There are outstanding command in the command queue of traffic-class #9 PBF_REG_YCMD_QS_OCCUPANCY_VOQ9 PBF: There are allocated blocks in BTB for VOQ9 PBF: There are packets in BTB belonging to traffic-class #9 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ9 PBF: Y command queue of VOQ10 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #10 PBF_REG_YCMD_QS_CMD_CNT_VOQ10 PBF: Y command queue of VOQ10 is not empty PBF: There are outstanding command in the command queue of traffic-class #10 PBF_REG_YCMD_QS_OCCUPANCY_VOQ10 PBF: There are allocated blocks in BTB for VOQ10 PBF: There are packets in BTB belonging to traffic-class #10 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ10 PBF: Y command queue of VOQ11 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #11 PBF_REG_YCMD_QS_CMD_CNT_VOQ11 PBF: Y command queue of VOQ11 is not empty PBF: There are outstanding command in the command queue of traffic-class #11 PBF_REG_YCMD_QS_OCCUPANCY_VOQ11 PBF: There are allocated blocks in BTB for VOQ11 PBF: There are packets in BTB belonging to traffic-class #11 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ11 PBF: Y command queue of VOQ12 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #12 PBF_REG_YCMD_QS_CMD_CNT_VOQ12 PBF: Y command queue of VOQ12 is not empty PBF: There are outstanding command in the command queue of traffic-class #12 PBF_REG_YCMD_QS_OCCUPANCY_VOQ12 PBF: There are allocated blocks in BTB for VOQ12 PBF: There are packets in BTB belonging to traffic-class #12 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ12 PBF: Y command queue of VOQ13 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #13 PBF_REG_YCMD_QS_CMD_CNT_VOQ13 PBF: Y command queue of VOQ13 is not empty PBF: There are outstanding command in the command queue of traffic-class #13 PBF_REG_YCMD_QS_OCCUPANCY_VOQ13 PBF: There are allocated blocks in BTB for VOQ13 PBF: There are packets in BTB belonging to traffic-class #13 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ13 PBF: Y command queue of VOQ14 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #14 PBF_REG_YCMD_QS_CMD_CNT_VOQ14 PBF: Y command queue of VOQ14 is not empty PBF: There are outstanding command in the command queue of traffic-class #14 PBF_REG_YCMD_QS_OCCUPANCY_VOQ14 PBF: There are allocated blocks in BTB for VOQ14 PBF: There are packets in BTB belonging to traffic-class #14 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ14 PBF: Y command queue of VOQ15 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #15 PBF_REG_YCMD_QS_CMD_CNT_VOQ15 PBF: Y command queue of VOQ15 is not empty PBF: There are outstanding command in the command queue of traffic-class #15 PBF_REG_YCMD_QS_OCCUPANCY_VOQ15 PBF: There are allocated blocks in BTB for VOQ15 PBF: There are packets in BTB belonging to traffic-class #15 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ15 PBF: Y command queue of VOQ16 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #16 PBF_REG_YCMD_QS_CMD_CNT_VOQ16 PBF: Y command queue of VOQ16 is not empty PBF: There are outstanding command in the command queue of traffic-class #16 PBF_REG_YCMD_QS_OCCUPANCY_VOQ16 PBF: There are allocated blocks in BTB for VOQ16 PBF: There are packets in BTB belonging to traffic-class #16 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ16 PBF: Y command queue of VOQ17 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #17 PBF_REG_YCMD_QS_CMD_CNT_VOQ17 PBF: Y command queue of VOQ17 is not empty PBF: There are outstanding command in the command queue of traffic-class #17 PBF_REG_YCMD_QS_OCCUPANCY_VOQ17 PBF: There are allocated blocks in BTB for VOQ17 PBF: There are packets in BTB belonging to traffic-class #17 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ17 PBF: Y command queue of VOQ18 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #18 PBF_REG_YCMD_QS_CMD_CNT_VOQ18 PBF: Y command queue of VOQ18 is not empty PBF: There are outstanding command in the command queue of traffic-class #18 PBF_REG_YCMD_QS_OCCUPANCY_VOQ18 PBF: There are allocated blocks in BTB for VOQ18 PBF: There are packets in BTB belonging to traffic-class #18 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ18 PBF: Y command queue of VOQ19 has commands which have not been processed PBF: There are outstanding command in the command queue of traffic-class #19 PBF_REG_YCMD_QS_CMD_CNT_VOQ19 PBF: Y command queue of VOQ19 is not empty PBF: There are outstanding command in the command queue of traffic-class #19 PBF_REG_YCMD_QS_OCCUPANCY_VOQ19 PBF: There are allocated blocks in BTB for VOQ19 PBF: There are packets in BTB belonging to traffic-class #19 PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ19 BTB: Interrupt status 1 is set BTB: Fatal BTB error BTB_REG_INT_STS_1 BTB: Interrupt status 2 is set BTB: Fatal BTB error BTB_REG_INT_STS_2 BTB: Interrupt status 3 is set BTB: Fatal BTB error BTB_REG_INT_STS_3 BTB Parity status is not 0 BTB_REG_PRTY_STS_H_0 BTB: Duplicated Write client FIFOs are not empty BTB: Duplicated Write client FIFOs are not empty BTB_REG_WC_DUP_EMPTY BTB: Duplicated Write client status is not 0 BTB: Duplicated Write client status is not 0 BTB_REG_WC_DUP_STATUS BTB: Write client 0 FIFOs are not empty (value != 0x1ffe) BTB: Write client FIFOs are not empty BTB_REG_WC_EMPTY_0 BTB: Write client bandwidth full IF is not 0 BTB: Global full to write clients is asserted (should be temporary due to big RAM BW limitations) BTB_REG_WC_BANDWIDTH_IF_FULL BTB: Read packet client IF full is not 0 BTB: One of the read clients asserted full to BTB BTB_REG_RC_PKT_IF_FULL BTB: Read packet client 0 FIFOs are not empty BTB: Read packet main port #0 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_0 BTB: Read packet client 1 FIFOs are not empty BTB: Read packet LB port #0 client 1 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_1 BTB: Read packet client 2 FIFOs are not empty BTB: Read packet main port #1 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_2 BTB: Read packet client 3 FIFOs are not empty BTB: Read packet LB port #1 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_3 BTB: Read SOP client FIFOs are not empty BTB: Read SOP client FIFOs are not empty BTB_REG_RC_SOP_EMPTY BTB: Link list arbiter is not empty BTB: Link list arbiter is not empty BTB_REG_LL_ARB_EMPTY BTB: Blocks occupancy > 46 BTB: Blocks occupancy > 46 BTB_REG_BLOCK_OCCUPANCY BTB: Read packet client state machines are not idle BTB: Read packet client state machines are not idle BTB_REG_RC_PKT_STATE BTB: Write client status is not 2 BTB: Write client status is not 2 BTB_REG_WC_STATUS_0 XSDM: Interrupt 0 is set XSDM: Fatal XSDM error XSDM_REG_INT_STS XSDM_REG_INP_QUEUE_ERR_VECT XSDM: Parity status is not 0 XSDM_REG_PRTY_STS_H_0 XSDM: QM asserts FULL to XSDM XSDM: FULL from QM is asserted XSDM_REG_QM_FULL XSDM: Interface to BRB is full XSDM: FULL to BRB is asserted XSDM_REG_RSP_BRB_IF_FULL XSDM: Interface from PXP is full XSDM: FULL to PXP is asserted XSDM_REG_RSP_PXP_IF_FULL XSDM: Interface from PXP is full XSDM: FULL from PXP is asserted XSDM_REG_DST_PXP_IF_FULL XSDM: internal ram IF is full XSDM: FULL from internal RAM is asserted XSDM_REG_DST_INT_RAM_IF_FULL XSDM: passive buffer IF is full XSDM: FULL from passive-buffer is asserted XSDM_REG_DST_PAS_BUF_IF_FULL XSDM_REG_INT_CMPL_PEND_EMPTY= 0 XSDM: The queue that holds internal write completion parameters is not empty XSDM_REG_INT_CMPL_PEND_EMPTY XSDM_REG_INT_CPRM_PEND_EMPTY= 0 XSDM: The queue that holds internal write completion parameters is not empty XSDM_REG_INT_CPRM_PEND_EMPTY XSDM: XSDM input queues are not all empty XSDM: XSDM input queues are not all empty XSDM_REG_QUEUE_EMPTY XSDM: XSDM_REG_DELAY_FIFO_EMPTY = 0 XSDM: The input delay FIFO is not empty XSDM_REG_DELAY_FIFO_EMPTY XSDM: XSDM_REG_RSP_PXP_RDATA_EMPTY = 0 XSDM: The queue that holds data from PXP is not empty XSDM_REG_RSP_PXP_RDATA_EMPTY XSDM: XSDM_REG_RSP_BRB_RDATA_EMPTY = 0 XSDM: The queue that holds BRB data is not empty XSDM_REG_RSP_BRB_RDATA_EMPTY XSDM: XSDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 XSDM: The queue that holds data from internal RAM is not empty XSDM_REG_RSP_INT_RAM_RDATA_EMPTY XSDM: XSDM_REG_RSP_BRB_PEND_EMPTY = 0 XSDM: There are outstanding BRB requests XSDM_REG_RSP_BRB_PEND_EMPTY XSDM: XSDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 XSDM: There are outstanding internal RAM requests XSDM_REG_RSP_INT_RAM_PEND_EMPTY XSDM: Immediate FIFO to PXP DST is not empty XSDM: The queue that holds immediate data intended to PXP is not empty XSDM_REG_DST_PXP_IMMED_EMPTY XSDM: XSDM_REG_DST_PXP_DST_PEND_EMPTY = 0 XSDM: The queue that holds data intended to PXP is not empty XSDM_REG_DST_PXP_DST_PEND_EMPTY XSDM: XSDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 XSDM: There are outstanding PXP requests XSDM_REG_DST_PXP_SRC_PEND_EMPTY XSDM: XSDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 XSDM: The queue that holds BRB source parameters is not empty XSDM_REG_DST_BRB_SRC_PEND_EMPTY XSDM: XSDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 XSDM: The queue that holds BRB source address parameters is not empty XSDM_REG_DST_BRB_SRC_ADDR_EMPTY XSDM: XSDM_REG_DST_PXP_LINK_EMPTY = 0 XSDM: The PXP requests linked-list is not empty XSDM_REG_DST_PXP_LINK_EMPTY XSDM: XSDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 XSDM: The queue that holds data intended to internal RAM is not empty XSDM_REG_DST_INT_RAM_WAIT_EMPTY XSDM: XSDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 XSDM: The queue that holds data intended to passive buffer is not empty XSDM_REG_DST_PAS_BUF_WAIT_EMPTY XSDM: XSDM_REG_SH_DELAY_EMPTY = 0 XSDM: The queue that holds the non-CM direct message completion parameters is not empty XSDM_REG_SH_DELAY_EMPTY XSDM: XSDM_REG_CM_DELAY_EMPTY = 0 XSDM: The queue that holds the CM direct message completion parameters is not empty XSDM_REG_CM_DELAY_EMPTY XSDM: XSDM_REG_CMSG_QUE_EMPTY = 0 XSDM: The queue that holds completion parameters is not empty XSDM_REG_CMSG_QUE_EMPTY XSDM: CCFC_LOAD_PEND_EMPTY = 0 XSDM: There are outstanding CCFC load requests XSDM_REG_CCFC_LOAD_PEND_EMPTY XSDM_REG_TCFC_LOAD_PEND_EMPTY= 0 XSDM: There are outstanding TCFC load requests XSDM_REG_TCFC_LOAD_PEND_EMPTY XSDM: XSDM_REG_ASYNC_HOST_EMPTY = 0 XSDM: There are pending async messages XSDM_REG_ASYNC_HOST_EMPTY XSDM_REG_PRM_FIFO_EMPTY= 0 XSDM: There are pending PRM completions XSDM_REG_PRM_FIFO_EMPTY YSDM: Interrupt 0 is set YSDM: Fatal YSDM error YSDM_REG_INT_STS YSDM_REG_INP_QUEUE_ERR_VECT YSDM: Parity status is not 0 YSDM_REG_PRTY_STS_H_0 YSDM: QM asserts FULL to YSDM YSDM: FULL from QM is asserted YSDM_REG_QM_FULL YSDM: Interface to BRB is full YSDM: FULL to BRB is asserted YSDM_REG_RSP_BRB_IF_FULL YSDM: Interface from PXP is full YSDM: FULL to PXP is asserted YSDM_REG_RSP_PXP_IF_FULL YSDM: Interface from PXP is full YSDM: FULL from PXP is asserted YSDM_REG_DST_PXP_IF_FULL YSDM: internal ram IF is full YSDM: FULL from internal RAM is asserted YSDM_REG_DST_INT_RAM_IF_FULL YSDM: passive buffer IF is full YSDM: FULL from passive-buffer is asserted YSDM_REG_DST_PAS_BUF_IF_FULL YSDM_REG_INT_CMPL_PEND_EMPTY= 0 YSDM: The queue that holds internal write completion parameters is not empty YSDM_REG_INT_CMPL_PEND_EMPTY YSDM_REG_INT_CPRM_PEND_EMPTY= 0 YSDM: The queue that holds internal write completion parameters is not empty YSDM_REG_INT_CPRM_PEND_EMPTY YSDM: YSDM input queues are not all empty YSDM: YSDM input queues are not all empty YSDM_REG_QUEUE_EMPTY YSDM: YSDM_REG_DELAY_FIFO_EMPTY = 0 YSDM: The input delay FIFO is not empty YSDM_REG_DELAY_FIFO_EMPTY YSDM: YSDM_REG_RSP_PXP_RDATA_EMPTY = 0 YSDM: The queue that holds data from PXP is not empty YSDM_REG_RSP_PXP_RDATA_EMPTY YSDM: YSDM_REG_RSP_BRB_RDATA_EMPTY = 0 YSDM: The queue that holds BRB data is not empty YSDM_REG_RSP_BRB_RDATA_EMPTY YSDM: YSDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 YSDM: The queue that holds data from internal RAM is not empty YSDM_REG_RSP_INT_RAM_RDATA_EMPTY YSDM: YSDM_REG_RSP_BRB_PEND_EMPTY = 0 YSDM: There are outstanding BRB requests YSDM_REG_RSP_BRB_PEND_EMPTY YSDM: YSDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 YSDM: There are outstanding internal RAM requests YSDM_REG_RSP_INT_RAM_PEND_EMPTY YSDM: Immediate FIFO to PXP DST is not empty YSDM: The queue that holds immediate data intended to PXP is not empty YSDM_REG_DST_PXP_IMMED_EMPTY YSDM: YSDM_REG_DST_PXP_DST_PEND_EMPTY = 0 YSDM: The queue that holds data intended to PXP is not empty YSDM_REG_DST_PXP_DST_PEND_EMPTY YSDM: YSDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 YSDM: There are outstanding PXP requests YSDM_REG_DST_PXP_SRC_PEND_EMPTY YSDM: YSDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 YSDM: The queue that holds BRB source parameters is not empty YSDM_REG_DST_BRB_SRC_PEND_EMPTY YSDM: YSDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 YSDM: The queue that holds BRB source address parameters is not empty YSDM_REG_DST_BRB_SRC_ADDR_EMPTY YSDM: YSDM_REG_DST_PXP_LINK_EMPTY = 0 YSDM: The PXP requests linked-list is not empty YSDM_REG_DST_PXP_LINK_EMPTY YSDM: YSDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 YSDM: The queue that holds data intended to internal RAM is not empty YSDM_REG_DST_INT_RAM_WAIT_EMPTY YSDM: YSDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 YSDM: The queue that holds data intended to passive buffer is not empty YSDM_REG_DST_PAS_BUF_WAIT_EMPTY YSDM: YSDM_REG_SH_DELAY_EMPTY = 0 YSDM: The queue that holds the non-CM direct message completion parameters is not empty YSDM_REG_SH_DELAY_EMPTY YSDM: YSDM_REG_CM_DELAY_EMPTY = 0 YSDM: The queue that holds the CM direct message completion parameters is not empty YSDM_REG_CM_DELAY_EMPTY YSDM: YSDM_REG_CMSG_QUE_EMPTY = 0 YSDM: The queue that holds completion parameters is not empty YSDM_REG_CMSG_QUE_EMPTY YSDM: CCFC_LOAD_PEND_EMPTY = 0 YSDM: There are outstanding CCFC load requests YSDM_REG_CCFC_LOAD_PEND_EMPTY YSDM_REG_TCFC_LOAD_PEND_EMPTY= 0 YSDM: There are outstanding TCFC load requests YSDM_REG_TCFC_LOAD_PEND_EMPTY YSDM: YSDM_REG_ASYNC_HOST_EMPTY = 0 YSDM: There are pending async messages YSDM_REG_ASYNC_HOST_EMPTY YSDM_REG_PRM_FIFO_EMPTY= 0 YSDM: There are pending PRM completions YSDM_REG_PRM_FIFO_EMPTY PSDM: Interrupt 0 is set PSDM: Fatal PSDM error PSDM_REG_INT_STS PSDM_REG_INP_QUEUE_ERR_VECT PSDM: Parity status is not 0 PSDM_REG_PRTY_STS_H_0 PSDM: QM asserts FULL to PSDM PSDM: FULL from QM is asserted PSDM_REG_QM_FULL PSDM: Interface to BRB is full PSDM: FULL to BRB is asserted PSDM_REG_RSP_BRB_IF_FULL PSDM: Interface from PXP is full PSDM: FULL to PXP is asserted PSDM_REG_RSP_PXP_IF_FULL PSDM: Interface from PXP is full PSDM: FULL from PXP is asserted PSDM_REG_DST_PXP_IF_FULL PSDM: internal ram IF is full PSDM: FULL from internal RAM is asserted PSDM_REG_DST_INT_RAM_IF_FULL PSDM: passive buffer IF is full PSDM: FULL from passive-buffer is asserted PSDM_REG_DST_PAS_BUF_IF_FULL PSDM_REG_INT_CMPL_PEND_EMPTY= 0 PSDM: The queue that holds internal write completion parameters is not empty PSDM_REG_INT_CMPL_PEND_EMPTY PSDM_REG_INT_CPRM_PEND_EMPTY= 0 PSDM: The queue that holds internal write completion parameters is not empty PSDM_REG_INT_CPRM_PEND_EMPTY PSDM: PSDM input queues are not all empty PSDM: PSDM input queues are not all empty PSDM_REG_QUEUE_EMPTY PSDM: PSDM_REG_DELAY_FIFO_EMPTY = 0 PSDM: The input delay FIFO is not empty PSDM_REG_DELAY_FIFO_EMPTY PSDM: PSDM_REG_RSP_PXP_RDATA_EMPTY = 0 PSDM: The queue that holds data from PXP is not empty PSDM_REG_RSP_PXP_RDATA_EMPTY PSDM: PSDM_REG_RSP_BRB_RDATA_EMPTY = 0 PSDM: The queue that holds BRB data is not empty PSDM_REG_RSP_BRB_RDATA_EMPTY PSDM: PSDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 PSDM: The queue that holds data from internal RAM is not empty PSDM_REG_RSP_INT_RAM_RDATA_EMPTY PSDM: PSDM_REG_RSP_BRB_PEND_EMPTY = 0 PSDM: There are outstanding BRB requests PSDM_REG_RSP_BRB_PEND_EMPTY PSDM: PSDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 PSDM: There are outstanding internal RAM requests PSDM_REG_RSP_INT_RAM_PEND_EMPTY PSDM: Immediate FIFO to PXP DST is not empty PSDM: The queue that holds immediate data intended to PXP is not empty PSDM_REG_DST_PXP_IMMED_EMPTY PSDM: PSDM_REG_DST_PXP_DST_PEND_EMPTY = 0 PSDM: The queue that holds data intended to PXP is not empty PSDM_REG_DST_PXP_DST_PEND_EMPTY PSDM: PSDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 PSDM: There are outstanding PXP requests PSDM_REG_DST_PXP_SRC_PEND_EMPTY PSDM: PSDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 PSDM: The queue that holds BRB source parameters is not empty PSDM_REG_DST_BRB_SRC_PEND_EMPTY PSDM: PSDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 PSDM: The queue that holds BRB source address parameters is not empty PSDM_REG_DST_BRB_SRC_ADDR_EMPTY PSDM: PSDM_REG_DST_PXP_LINK_EMPTY = 0 PSDM: The PXP requests linked-list is not empty PSDM_REG_DST_PXP_LINK_EMPTY PSDM: PSDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 PSDM: The queue that holds data intended to internal RAM is not empty PSDM_REG_DST_INT_RAM_WAIT_EMPTY PSDM: PSDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 PSDM: The queue that holds data intended to passive buffer is not empty PSDM_REG_DST_PAS_BUF_WAIT_EMPTY PSDM: PSDM_REG_SH_DELAY_EMPTY = 0 PSDM: The queue that holds the non-CM direct message completion parameters is not empty PSDM_REG_SH_DELAY_EMPTY PSDM: PSDM_REG_CM_DELAY_EMPTY = 0 PSDM: The queue that holds the CM direct message completion parameters is not empty PSDM_REG_CM_DELAY_EMPTY PSDM: PSDM_REG_CMSG_QUE_EMPTY = 0 PSDM: The queue that holds completion parameters is not empty PSDM_REG_CMSG_QUE_EMPTY PSDM: CCFC_LOAD_PEND_EMPTY = 0 PSDM: There are outstanding CCFC load requests PSDM_REG_CCFC_LOAD_PEND_EMPTY PSDM_REG_TCFC_LOAD_PEND_EMPTY= 0 PSDM: There are outstanding TCFC load requests PSDM_REG_TCFC_LOAD_PEND_EMPTY PSDM: PSDM_REG_ASYNC_HOST_EMPTY = 0 PSDM: There are pending async messages PSDM_REG_ASYNC_HOST_EMPTY PSDM_REG_PRM_FIFO_EMPTY= 0 PSDM: There are pending PRM completions PSDM_REG_PRM_FIFO_EMPTY TSDM: Interrupt 0 is set TSDM: Fatal TSDM error TSDM_REG_INT_STS TSDM_REG_INP_QUEUE_ERR_VECT TSDM: Parity status is not 0 TSDM_REG_PRTY_STS_H_0 TSDM: QM asserts FULL to TSDM TSDM: FULL from QM is asserted TSDM_REG_QM_FULL TSDM: Interface to BRB is full TSDM: FULL to BRB is asserted TSDM_REG_RSP_BRB_IF_FULL TSDM: Interface from PXP is full TSDM: FULL to PXP is asserted TSDM_REG_RSP_PXP_IF_FULL TSDM: Interface from PXP is full TSDM: FULL from PXP is asserted TSDM_REG_DST_PXP_IF_FULL TSDM: internal ram IF is full TSDM: FULL from internal RAM is asserted TSDM_REG_DST_INT_RAM_IF_FULL TSDM: passive buffer IF is full TSDM: FULL from passive-buffer is asserted TSDM_REG_DST_PAS_BUF_IF_FULL TSDM_REG_INT_CMPL_PEND_EMPTY= 0 TSDM: The queue that holds internal write completion parameters is not empty TSDM_REG_INT_CMPL_PEND_EMPTY TSDM_REG_INT_CPRM_PEND_EMPTY= 0 TSDM: The queue that holds internal write completion parameters is not empty TSDM_REG_INT_CPRM_PEND_EMPTY TSDM: TSDM input queues are not all empty TSDM: TSDM input queues are not all empty TSDM_REG_QUEUE_EMPTY TSDM: TSDM_REG_DELAY_FIFO_EMPTY = 0 TSDM: The input delay FIFO is not empty TSDM_REG_DELAY_FIFO_EMPTY TSDM: TSDM_REG_RSP_PXP_RDATA_EMPTY = 0 TSDM: The queue that holds data from PXP is not empty TSDM_REG_RSP_PXP_RDATA_EMPTY TSDM: TSDM_REG_RSP_BRB_RDATA_EMPTY = 0 TSDM: The queue that holds BRB data is not empty TSDM_REG_RSP_BRB_RDATA_EMPTY TSDM: TSDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 TSDM: The queue that holds data from internal RAM is not empty TSDM_REG_RSP_INT_RAM_RDATA_EMPTY TSDM: TSDM_REG_RSP_BRB_PEND_EMPTY = 0 TSDM: There are outstanding BRB requests TSDM_REG_RSP_BRB_PEND_EMPTY TSDM: TSDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 TSDM: There are outstanding internal RAM requests TSDM_REG_RSP_INT_RAM_PEND_EMPTY TSDM: Immediate FIFO to PXP DST is not empty TSDM: The queue that holds immediate data intended to PXP is not empty TSDM_REG_DST_PXP_IMMED_EMPTY TSDM: TSDM_REG_DST_PXP_DST_PEND_EMPTY = 0 TSDM: The queue that holds data intended to PXP is not empty TSDM_REG_DST_PXP_DST_PEND_EMPTY TSDM: TSDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 TSDM: There are outstanding PXP requests TSDM_REG_DST_PXP_SRC_PEND_EMPTY TSDM: TSDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 TSDM: The queue that holds BRB source parameters is not empty TSDM_REG_DST_BRB_SRC_PEND_EMPTY TSDM: TSDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 TSDM: The queue that holds BRB source address parameters is not empty TSDM_REG_DST_BRB_SRC_ADDR_EMPTY TSDM: TSDM_REG_DST_PXP_LINK_EMPTY = 0 TSDM: The PXP requests linked-list is not empty TSDM_REG_DST_PXP_LINK_EMPTY TSDM: TSDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 TSDM: The queue that holds data intended to internal RAM is not empty TSDM_REG_DST_INT_RAM_WAIT_EMPTY TSDM: TSDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 TSDM: The queue that holds data intended to passive buffer is not empty TSDM_REG_DST_PAS_BUF_WAIT_EMPTY TSDM: TSDM_REG_SH_DELAY_EMPTY = 0 TSDM: The queue that holds the non-CM direct message completion parameters is not empty TSDM_REG_SH_DELAY_EMPTY TSDM: TSDM_REG_CM_DELAY_EMPTY = 0 TSDM: The queue that holds the CM direct message completion parameters is not empty TSDM_REG_CM_DELAY_EMPTY TSDM: TSDM_REG_CMSG_QUE_EMPTY = 0 TSDM: The queue that holds completion parameters is not empty TSDM_REG_CMSG_QUE_EMPTY TSDM: CCFC_LOAD_PEND_EMPTY = 0 TSDM: There are outstanding CCFC load requests TSDM_REG_CCFC_LOAD_PEND_EMPTY TSDM_REG_TCFC_LOAD_PEND_EMPTY= 0 TSDM: There are outstanding TCFC load requests TSDM_REG_TCFC_LOAD_PEND_EMPTY TSDM: TSDM_REG_ASYNC_HOST_EMPTY = 0 TSDM: There are pending async messages TSDM_REG_ASYNC_HOST_EMPTY TSDM_REG_PRM_FIFO_EMPTY= 0 TSDM: There are pending PRM completions TSDM_REG_PRM_FIFO_EMPTY MSDM: Interrupt 0 is set MSDM: Fatal MSDM error MSDM_REG_INT_STS MSDM_REG_INP_QUEUE_ERR_VECT MSDM: Parity status is not 0 MSDM_REG_PRTY_STS_H_0 MSDM: QM asserts FULL to MSDM MSDM: FULL from QM is asserted MSDM_REG_QM_FULL MSDM: Interface to BRB is full MSDM: FULL to BRB is asserted MSDM_REG_RSP_BRB_IF_FULL MSDM: Interface from PXP is full MSDM: FULL to PXP is asserted MSDM_REG_RSP_PXP_IF_FULL MSDM: Interface from PXP is full MSDM: FULL from PXP is asserted MSDM_REG_DST_PXP_IF_FULL MSDM: internal ram IF is full MSDM: FULL from internal RAM is asserted MSDM_REG_DST_INT_RAM_IF_FULL MSDM: passive buffer IF is full MSDM: FULL from passive-buffer is asserted MSDM_REG_DST_PAS_BUF_IF_FULL MSDM_REG_INT_CMPL_PEND_EMPTY= 0 MSDM: The queue that holds internal write completion parameters is not empty MSDM_REG_INT_CMPL_PEND_EMPTY MSDM_REG_INT_CPRM_PEND_EMPTY= 0 MSDM: The queue that holds internal write completion parameters is not empty MSDM_REG_INT_CPRM_PEND_EMPTY MSDM: MSDM input queues are not all empty MSDM: MSDM input queues are not all empty MSDM_REG_QUEUE_EMPTY MSDM: MSDM_REG_DELAY_FIFO_EMPTY = 0 MSDM: The input delay FIFO is not empty MSDM_REG_DELAY_FIFO_EMPTY MSDM: MSDM_REG_RSP_PXP_RDATA_EMPTY = 0 MSDM: The queue that holds data from PXP is not empty MSDM_REG_RSP_PXP_RDATA_EMPTY MSDM: MSDM_REG_RSP_BRB_RDATA_EMPTY = 0 MSDM: The queue that holds BRB data is not empty MSDM_REG_RSP_BRB_RDATA_EMPTY MSDM: MSDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 MSDM: The queue that holds data from internal RAM is not empty MSDM_REG_RSP_INT_RAM_RDATA_EMPTY MSDM: MSDM_REG_RSP_BRB_PEND_EMPTY = 0 MSDM: There are outstanding BRB requests MSDM_REG_RSP_BRB_PEND_EMPTY MSDM: MSDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 MSDM: There are outstanding internal RAM requests MSDM_REG_RSP_INT_RAM_PEND_EMPTY MSDM: Immediate FIFO to PXP DST is not empty MSDM: The queue that holds immediate data intended to PXP is not empty MSDM_REG_DST_PXP_IMMED_EMPTY MSDM: MSDM_REG_DST_PXP_DST_PEND_EMPTY = 0 MSDM: The queue that holds data intended to PXP is not empty MSDM_REG_DST_PXP_DST_PEND_EMPTY MSDM: MSDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 MSDM: There are outstanding PXP requests MSDM_REG_DST_PXP_SRC_PEND_EMPTY MSDM: MSDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 MSDM: The queue that holds BRB source parameters is not empty MSDM_REG_DST_BRB_SRC_PEND_EMPTY MSDM: MSDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 MSDM: The queue that holds BRB source address parameters is not empty MSDM_REG_DST_BRB_SRC_ADDR_EMPTY MSDM: MSDM_REG_DST_PXP_LINK_EMPTY = 0 MSDM: The PXP requests linked-list is not empty MSDM_REG_DST_PXP_LINK_EMPTY MSDM: MSDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 MSDM: The queue that holds data intended to internal RAM is not empty MSDM_REG_DST_INT_RAM_WAIT_EMPTY MSDM: MSDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 MSDM: The queue that holds data intended to passive buffer is not empty MSDM_REG_DST_PAS_BUF_WAIT_EMPTY MSDM: MSDM_REG_SH_DELAY_EMPTY = 0 MSDM: The queue that holds the non-CM direct message completion parameters is not empty MSDM_REG_SH_DELAY_EMPTY MSDM: MSDM_REG_CM_DELAY_EMPTY = 0 MSDM: The queue that holds the CM direct message completion parameters is not empty MSDM_REG_CM_DELAY_EMPTY MSDM: MSDM_REG_CMSG_QUE_EMPTY = 0 MSDM: The queue that holds completion parameters is not empty MSDM_REG_CMSG_QUE_EMPTY MSDM: CCFC_LOAD_PEND_EMPTY = 0 MSDM: There are outstanding CCFC load requests MSDM_REG_CCFC_LOAD_PEND_EMPTY MSDM_REG_TCFC_LOAD_PEND_EMPTY= 0 MSDM: There are outstanding TCFC load requests MSDM_REG_TCFC_LOAD_PEND_EMPTY MSDM: MSDM_REG_ASYNC_HOST_EMPTY = 0 MSDM: There are pending async messages MSDM_REG_ASYNC_HOST_EMPTY MSDM_REG_PRM_FIFO_EMPTY= 0 MSDM: There are pending PRM completions MSDM_REG_PRM_FIFO_EMPTY USDM: Interrupt 0 is set USDM: Fatal USDM error USDM_REG_INT_STS USDM_REG_INP_QUEUE_ERR_VECT USDM: Parity status is not 0 USDM_REG_PRTY_STS_H_0 USDM: QM asserts FULL to USDM USDM: FULL from QM is asserted USDM_REG_QM_FULL USDM: Interface to BRB is full USDM: FULL to BRB is asserted USDM_REG_RSP_BRB_IF_FULL USDM: Interface from PXP is full USDM: FULL to PXP is asserted USDM_REG_RSP_PXP_IF_FULL USDM: Interface from PXP is full USDM: FULL from PXP is asserted USDM_REG_DST_PXP_IF_FULL USDM: internal ram IF is full USDM: FULL from internal RAM is asserted USDM_REG_DST_INT_RAM_IF_FULL USDM: passive buffer IF is full USDM: FULL from passive-buffer is asserted USDM_REG_DST_PAS_BUF_IF_FULL USDM_REG_INT_CMPL_PEND_EMPTY= 0 USDM: The queue that holds internal write completion parameters is not empty USDM_REG_INT_CMPL_PEND_EMPTY USDM_REG_INT_CPRM_PEND_EMPTY= 0 USDM: The queue that holds internal write completion parameters is not empty USDM_REG_INT_CPRM_PEND_EMPTY USDM: USDM input queues are not all empty USDM: USDM input queues are not all empty USDM_REG_QUEUE_EMPTY USDM: USDM_REG_DELAY_FIFO_EMPTY = 0 USDM: The input delay FIFO is not empty USDM_REG_DELAY_FIFO_EMPTY USDM: USDM_REG_RSP_PXP_RDATA_EMPTY = 0 USDM: The queue that holds data from PXP is not empty USDM_REG_RSP_PXP_RDATA_EMPTY USDM: USDM_REG_RSP_BRB_RDATA_EMPTY = 0 USDM: The queue that holds BRB data is not empty USDM_REG_RSP_BRB_RDATA_EMPTY USDM: USDM_REG_RSP_INT_RAM_RDATA_EMPTY = 0 USDM: The queue that holds data from internal RAM is not empty USDM_REG_RSP_INT_RAM_RDATA_EMPTY USDM: USDM_REG_RSP_BRB_PEND_EMPTY = 0 USDM: There are outstanding BRB requests USDM_REG_RSP_BRB_PEND_EMPTY USDM: USDM_REG_RSP_INT_RAM_PEND_EMPTY = 0 USDM: There are outstanding internal RAM requests USDM_REG_RSP_INT_RAM_PEND_EMPTY USDM: Immediate FIFO to PXP DST is not empty USDM: The queue that holds immediate data intended to PXP is not empty USDM_REG_DST_PXP_IMMED_EMPTY USDM: USDM_REG_DST_PXP_DST_PEND_EMPTY = 0 USDM: The queue that holds data intended to PXP is not empty USDM_REG_DST_PXP_DST_PEND_EMPTY USDM: USDM_REG_DST_PXP_SRC_PEND_EMPTY = 0 USDM: There are outstanding PXP requests USDM_REG_DST_PXP_SRC_PEND_EMPTY USDM: USDM_REG_DST_BRB_SRC_PEND_EMPTY = 0 USDM: The queue that holds BRB source parameters is not empty USDM_REG_DST_BRB_SRC_PEND_EMPTY USDM: USDM_REG_DST_BRB_SRC_ADDR_EMPTY = 0 USDM: The queue that holds BRB source address parameters is not empty USDM_REG_DST_BRB_SRC_ADDR_EMPTY USDM: USDM_REG_DST_PXP_LINK_EMPTY = 0 USDM: The PXP requests linked-list is not empty USDM_REG_DST_PXP_LINK_EMPTY USDM: USDM_REG_DST_INT_RAM_WAIT_EMPTY = 0 USDM: The queue that holds data intended to internal RAM is not empty USDM_REG_DST_INT_RAM_WAIT_EMPTY USDM: USDM_REG_DST_PAS_BUF_WAIT_EMPTY = 0 USDM: The queue that holds data intended to passive buffer is not empty USDM_REG_DST_PAS_BUF_WAIT_EMPTY USDM: USDM_REG_SH_DELAY_EMPTY = 0 USDM: The queue that holds the non-CM direct message completion parameters is not empty USDM_REG_SH_DELAY_EMPTY USDM: USDM_REG_CM_DELAY_EMPTY = 0 USDM: The queue that holds the CM direct message completion parameters is not empty USDM_REG_CM_DELAY_EMPTY USDM: USDM_REG_CMSG_QUE_EMPTY = 0 USDM: The queue that holds completion parameters is not empty USDM_REG_CMSG_QUE_EMPTY USDM: CCFC_LOAD_PEND_EMPTY = 0 USDM: There are outstanding CCFC load requests USDM_REG_CCFC_LOAD_PEND_EMPTY USDM_REG_TCFC_LOAD_PEND_EMPTY= 0 USDM: There are outstanding TCFC load requests USDM_REG_TCFC_LOAD_PEND_EMPTY USDM: USDM_REG_ASYNC_HOST_EMPTY = 0 USDM: There are pending async messages USDM_REG_ASYNC_HOST_EMPTY USDM_REG_PRM_FIFO_EMPTY= 0 USDM: There are pending PRM completions USDM_REG_PRM_FIFO_EMPTY XCM: Interrupt status 0 is not 0 XCM: There is an interrupt on register 0 XCM_REG_INT_STS_0 XCM: Interrupt status 1 is not 0 XCM: There is an interrupt on register 1 XCM_REG_INT_STS_1 XCM: Interrupt status 2 is not 0 XCM: There is an interrupt on register 2 XCM_REG_INT_STS_2 XCM_REG_QM_ACT_ST_CNT_ERR_DETAILS XCM: Parity status 0 is not 0 XCM_REG_PRTY_STS_H_0 XCM: Parity status 1 is not 0 XCM_REG_PRTY_STS_H_1 XCM: Input violation in message first descriptor XCM_REG_FI_DESC_INPUT_VIOLATE XCM: Aggregation Connection IA part buffer is not empty XCM_REG_IA_AGG_CON_PART_FILL_LVL XCM: STORM Connection IA part buffer is not empty XCM_REG_IA_SM_CON_PART_FILL_LVL XCM: Transparent part buffer is not empty XCM_REG_IA_TRANS_PART_FILL_LVL XCM: XX_FREE_CNT is different than reset value XCM: There are messages in the XX RAM XCM_REG_XX_FREE_CNT XCM: XX protection CAM is not empty XCM: XX CAM has active lcids XCM_REG_XX_LCID_CAM_FILL_LVL XCM: there is locked LCID in XX XCM: has locked lcids in xxLock XCM_REG_XX_LOCK_CNT XCM: XX Connection bypass table is not empty XCM_REG_XX_CBYP_TBL_FILL_LVL XCM: Aggregation Connection FIC buffer is not empty XCM_REG_AGG_CON_FIC_BUF_FILL_LVL XCM: STORM Connection FIC buffer is not empty XCM_REG_SM_CON_FIC_BUF_FILL_LVL XCM: In-process table is not empty XCM_REG_IN_PRCS_TBL_FILL_LVL XCM: CCFC_INIT_CRD is different than reset value XCM: There are pending messages in XCM->CCFC interface XCM_REG_CCFC_INIT_CRD XCM: XQM_INIT_CRD0 is different than reset value XCM: There are pending messages in XCM->QM interface XCM_REG_QM_INIT_CRD0 XCM: XQM_INIT_CRD1 is different than reset value XCM: There are pending messages in XCM->QM interface XCM_REG_QM_INIT_CRD1 XCM: TM_INIT_CRD is different than reset value XCM: There are pending messages in XCM->TM interface XCM_REG_TM_INIT_CRD XCM: FIC_INIT_CRD is different than reset value XCM: There are pending messages in XCM->XSEM interface XCM_REG_FIC_INIT_CRD XCM: MSDM declared message length unequal to actual XCM_REG_MSDM_LENGTH_MIS XCM: XSDM declared message length unequal to actual XCM_REG_XSDM_LENGTH_MIS XCM: YSDM declared message length unequal to actual XCM_REG_YSDM_LENGTH_MIS XCM: DORQ declared message length unequal to actual XCM_REG_DORQ_LENGTH_MIS XCM: PBF declared message length unequal to actual XCM_REG_PBF_LENGTH_MIS XCM: QM_P input stage buffer is not empty XCM: There are pending messages in QM(primary)->XCM interface XCM_REG_IS_QM_P_FILL_LVL XCM: QM_S input stage buffer is not empty XCM: There are pending messages in QM(secondary)->XCM interface XCM_REG_IS_QM_S_FILL_LVL XCM: TM input stage buffer is not empty XCM: There are pending messages in TM->XCM interface XCM_REG_IS_TM_FILL_LVL XCM: Local STORM input stage buffer is not empty XCM: There are pending messages in XSEM->XCM interface XCM_REG_IS_STORM_FILL_LVL XCM: MSDM input stage buffer is not empty XCM: There are pending messages in MSDM->XCM interface XCM_REG_IS_MSDM_FILL_LVL XCM: XSDM input stage buffer is not empty XCM: There are pending messages in XSDM->XCM interface XCM_REG_IS_XSDM_FILL_LVL XCM: YSDM input stage buffer is not empty XCM: There are pending messages in YSDM->XCM interface XCM_REG_IS_YSDM_FILL_LVL XCM: MSEM input stage buffer is not empty XCM: There are pending messages in MSEM->XCM interface XCM_REG_IS_MSEM_FILL_LVL XCM: USEM input stage buffer is not empty XCM: There are pending messages in USEM->XCM interface XCM_REG_IS_USEM_FILL_LVL XCM: YSEM input stage buffer is not empty XCM: There are pending messages in YSEM->XCM interface XCM_REG_IS_YSEM_FILL_LVL XCM: DORQ input stage buffer is not empty XCM: There are pending messages in DORQ->XCM interface XCM_REG_IS_DORQ_FILL_LVL XCM: PBF input stage buffer is not empty XCM: There are pending messages in PBF->XCM interface XCM_REG_IS_PBF_FILL_LVL YCM: Interrupt status 0 is not 0 YCM: There is an interrupt on register 0 YCM_REG_INT_STS_0 YCM: Interrupt status 1 is not 0 YCM: There is an interrupt on register 1 YCM_REG_INT_STS_1 YCM: Parity status 0 is not 0 YCM_REG_PRTY_STS_H_0 YCM: Parity status 1 is not 0 YCM_REG_PRTY_STS_H_1 YCM: Input violation in message first descriptor YCM_REG_FI_DESC_INPUT_VIOLATE YCM: Input violation in message second descriptor YCM_REG_SE_DESC_INPUT_VIOLATE YCM: STORM Connection IA part buffer is not empty YCM_REG_IA_SM_CON_PART_FILL_LVL YCM: Aggregation Task IA part buffer is not empty YCM_REG_IA_AGG_TASK_PART_FILL_LVL YCM: STORM Task IA part buffer is not empty YCM_REG_IA_SM_TASK_PART_FILL_LVL YCM: Transparent part buffer is not empty YCM_REG_IA_TRANS_PART_FILL_LVL YCM: XX_FREE_CNT is different than reset value YCM: There are messages in the XX RAM YCM_REG_XX_FREE_CNT YCM: XX protection CAM is not empty YCM: XX CAM has active lcids YCM_REG_XX_LCID_CAM_FILL_LVL YCM: there is locked LCID in XX YCM: has locked lcids in xxLock YCM_REG_XX_LOCK_CNT YCM: XX Connection bypass table is not empty YCM_REG_XX_CBYP_TBL_FILL_LVL YCM: XX Tbypass Table is not empty YCM_REG_XX_TBYP_TBL_FILL_LVL YCM: XX Task bypass table is not empty YCM_REG_XX_TBYP_TBL_FILL_LVL YCM: STORM Connection FIC buffer is not empty YCM_REG_SM_CON_FIC_BUF_FILL_LVL YCM: Aggregation Task FIC buffer is not empty YCM_REG_AGG_TASK_FIC_BUF_FILL_LVL YCM: STORM Task FIC buffer is not empty YCM_REG_SM_TASK_FIC_BUF_FILL_LVL YCM: In-process table is not empty YCM_REG_IN_PRCS_TBL_FILL_LVL YCM: CCFC_INIT_CRD is different than reset value YCM: There are pending messages in YCM->CCFC interface YCM_REG_CCFC_INIT_CRD YCM: TCFC_INIT_CRD is different than reset value YCM: There are pending messages in YCM->TCFC interface YCM_REG_TCFC_INIT_CRD YCM: QM_INIT_CRD0 is different than reset value YCM: There are pending messages in YCM->QM interface YCM_REG_QM_INIT_CRD0 YCM: FIC_INIT_CRD is different than reset value YCM: There are pending messages in YCM->YSEM interface YCM_REG_FIC_INIT_CRD YCM: MSDM declared message length unequal to actual YCM_REG_MSDM_LENGTH_MIS YCM: YSDM declared message length unequal to actual YCM_REG_YSDM_LENGTH_MIS YCM: PBF declared message length unequal to actual YCM_REG_PBF_LENGTH_MIS YCM: XYLD declared message length unequal to actual YCM_REG_XYLD_LENGTH_MIS YCM: QM_P input stage buffer is not empty YCM: There are pending messages in QM(primary)->YCM interface YCM_REG_IS_QM_P_FILL_LVL YCM: QM_S input stage buffer is not empty YCM: There are pending messages in QM(secondary)->YCM interface YCM_REG_IS_QM_S_FILL_LVL YCM: Local STORM input stage buffer is not empty YCM: There are pending messages in YSEM->YCM interface YCM_REG_IS_STORM_FILL_LVL YCM: MSDM input stage buffer is not empty YCM: There are pending messages in MSDM->YCM interface YCM_REG_IS_MSDM_FILL_LVL YCM: YSDM input stage buffer is not empty YCM: There are pending messages in YSDM->YCM interface YCM_REG_IS_YSDM_FILL_LVL YCM: XYLD input stage buffer is not empty YCM: There are pending messages in XYLD->YCM interface YCM_REG_IS_XYLD_FILL_LVL YCM: MSEM input stage buffer is not empty YCM: There are pending messages in MSEM->YCM interface YCM_REG_IS_MSEM_FILL_LVL YCM: USEM input stage buffer is not empty YCM: There are pending messages in USEM->YCM interface YCM_REG_IS_USEM_FILL_LVL YCM: PBF input stage buffer is not empty YCM: There are pending messages in PBF->YCM interface YCM_REG_IS_PBF_FILL_LVL PCM: Interrupt status 0 is not 0 PCM: There is an interrupt on register 0 PCM_REG_INT_STS_0 PCM: Interrupt status 1 is not 0 PCM: There is an interrupt on register 1 PCM_REG_INT_STS_1 PCM: Parity status is not 0 PCM_REG_PRTY_STS_H_0 PCM: Input violation in message first descriptor PCM_REG_FI_DESC_INPUT_VIOLATE PCM: STORM Connection IA part buffer is not empty PCM_REG_IA_SM_CON_PART_FILL_LVL PCM: Transparent part buffer is not empty PCM_REG_IA_TRANS_PART_FILL_LVL PCM: XX_FREE_CNT is different than reset value PCM: There are messages in the XX RAM PCM_REG_XX_FREE_CNT PCM: XX protection CAM is not empty PCM: XX CAM has active lcids PCM_REG_XX_LCID_CAM_FILL_LVL PCM: there is locked LCID in XX PCM: has locked lcids in xxLock PCM_REG_XX_LOCK_CNT PCM: STORM Connection FIC buffer is not empty PCM_REG_SM_CON_FIC_BUF_FILL_LVL PCM: In-process table is not empty PCM_REG_IN_PRCS_TBL_FILL_LVL PCM: CCFC_INIT_CRD is different than reset value PCM: There are pending messages in PCM->CCFC interface PCM_REG_CCFC_INIT_CRD PCM: FIC_INIT_CRD is different than reset value PCM: There are pending messages in PCM->PSEM interface PCM_REG_FIC_INIT_CRD PCM: PSDM declared message length unequal to actual PCM_REG_PSDM_LENGTH_MIS PCM: PBF declared message length unequal to actual PCM_REG_PBF_LENGTH_MIS PCM: Local STORM input stage buffer is not empty PCM_REG_IS_STORM_FILL_LVL PCM: PSDM input stage buffer is not empty PCM_REG_IS_PSDM_FILL_LVL PCM: PBF input stage buffer is not empty PCM_REG_IS_PBF_FILL_LVL TCM: Interrupt status 0 is not 0 TCM: There is an interrupt on register 0 TCM_REG_INT_STS_0 TCM: Interrupt status 1 is not 0 TCM: There is an interrupt on register 1 TCM_REG_INT_STS_1 TCM: Parity status 0 is not 0 TCM_REG_PRTY_STS_H_0 TCM: Parity status 1 is not 0 TCM_REG_PRTY_STS_H_1 TCM: Input violation in message first descriptor TCM_REG_FI_DESC_INPUT_VIOLATE TCM: Input violation in message second descriptor TCM_REG_SE_DESC_INPUT_VIOLATE TCM: Aggregation Connection IA part buffer is not empty TCM_REG_IA_AGG_CON_PART_FILL_LVL TCM: STORM Connection IA part buffer is not empty TCM_REG_IA_SM_CON_PART_FILL_LVL TCM: Aggregation Task IA part buffer is not empty TCM_REG_IA_AGG_TASK_PART_FILL_LVL TCM: STORM Task IA part buffer is not empty TCM_REG_IA_SM_TASK_PART_FILL_LVL TCM: Transparent part buffer is not empty TCM_REG_IA_TRANS_PART_FILL_LVL TCM: XX_FREE_CNT is different than reset value TCM: There are messages in the XX RAM TCM_REG_XX_FREE_CNT TCM: XX protection CAM is not empty TCM: XX CAM has active lcids TCM_REG_XX_LCID_CAM_FILL_LVL TCM: there is locked LCID in XX TCM: has locked lcids in xxLock TCM_REG_XX_LOCK_CNT TCM: XX Connection bypass table is not empty TCM_REG_XX_CBYP_TBL_FILL_LVL TCM: XX Tbypass Table is not empty TCM_REG_XX_TBYP_TBL_FILL_LVL TCM: XX Task bypass table is not empty TCM_REG_XX_TBYP_TBL_FILL_LVL TCM: Aggregation Connection FIC buffer is not empty TCM_REG_AGG_CON_FIC_BUF_FILL_LVL TCM: STORM Connection FIC buffer is not empty TCM_REG_SM_CON_FIC_BUF_FILL_LVL TCM: Aggregation Task FIC buffer is not empty TCM_REG_AGG_TASK_FIC_BUF_FILL_LVL TCM: STORM Task FIC buffer is not empty TCM_REG_SM_TASK_FIC_BUF_FILL_LVL TCM: In-process table is not empty TCM_REG_IN_PRCS_TBL_FILL_LVL TCM: CCFC_INIT_CRD is different than reset value TCM: There are pending messages in TCM->CCFC interface TCM_REG_CCFC_INIT_CRD TCM: TCFC_INIT_CRD is different than reset value TCM: There are pending messages in TCM->TCFC interface TCM_REG_TCFC_INIT_CRD TCM: QM_INIT_CRD0 is different than reset value TCM: There are pending messages in TCM->QM interface TCM_REG_QM_INIT_CRD0 TCM: TM_INIT_CRD is different than reset value TCM: There are pending messages in TCM->TM interface TCM_REG_TM_INIT_CRD TCM: FIC_INIT_CRD is different than reset value TCM: There are pending messages in TCM->TSEM interface TCM_REG_FIC_INIT_CRD TCM: TSDM declared message length unequal to actual TCM_REG_TSDM_LENGTH_MIS TCM: DORQ declared message length unequal to actual TCM_REG_DORQ_LENGTH_MIS TCM: PBF declared message length unequal to actual TCM_REG_PBF_LENGTH_MIS TCM: PRS declared message length unequal to actual TCM_REG_PRS_LENGTH_MIS TCM: QM_P input stage buffer is not empty TCM: There are pending messages in QM(primary)->TCM interface TCM_REG_IS_QM_P_FILL_LVL TCM: QM_S input stage buffer is not empty TCM: There are pending messages in QM(secondary)->TCM interface TCM_REG_IS_QM_S_FILL_LVL TCM: TM input stage buffer is not empty TCM: There are pending messages in TM->TCM interface TCM_REG_IS_TM_FILL_LVL TCM: Local STORM input stage buffer is not empty TCM: There are pending messages in TSEM->TCM interface TCM_REG_IS_STORM_FILL_LVL TCM: TSDM input stage buffer is not empty TCM: There are pending messages in TSDM->TCM interface TCM_REG_IS_TSDM_FILL_LVL TCM: MSEM input stage buffer is not empty TCM: There are pending messages in MSEM->TCM interface TCM_REG_IS_MSEM_FILL_LVL TCM: DORQ input stage buffer is not empty TCM: There are pending messages in DORQ->TCM interface TCM_REG_IS_DORQ_FILL_LVL TCM: PBF input stage buffer is not empty TCM: There are pending messages in PBF->TCM interface TCM_REG_IS_PBF_FILL_LVL TCM: PRS input stage buffer is not empty TCM: There are pending messages in PRS->TCM interface TCM_REG_IS_PRS_FILL_LVL MCM: Interrupt status 0 is not 0 MCM: There is an interrupt on register 0 MCM_REG_INT_STS_0 MCM: Interrupt status 1 is not 0 MCM: There is an interrupt on register 1 MCM_REG_INT_STS_1 MCM: Parity status 0 is not 0 MCM_REG_PRTY_STS_H_0 MCM: Parity status 1 is not 0 MCM_REG_PRTY_STS_H_1 MCM: Input violation in message first descriptor MCM_REG_FI_DESC_INPUT_VIOLATE MCM: Input violation in message second descriptor MCM_REG_SE_DESC_INPUT_VIOLATE MCM: Aggregation Connection IA part buffer is not empty MCM_REG_IA_AGG_CON_PART_FILL_LVL MCM: STORM Connection IA part buffer is not empty MCM_REG_IA_SM_CON_PART_FILL_LVL MCM: Aggregation Task IA part buffer is not empty MCM_REG_IA_AGG_TASK_PART_FILL_LVL MCM: STORM Task IA part buffer is not empty MCM_REG_IA_SM_TASK_PART_FILL_LVL MCM: Transparent part buffer is not empty MCM_REG_IA_TRANS_PART_FILL_LVL MCM: XX_FREE_CNT is different than reset value MCM: There are messages in the XX RAM MCM_REG_XX_FREE_CNT MCM: XX protection CAM is not empty MCM: XX CAM has active lcids MCM_REG_XX_LCID_CAM_FILL_LVL MCM: there is locked LCID in XX MCM: has locked lcids in xxLock MCM_REG_XX_LOCK_CNT MCM: XX Connection bypass table is not empty MCM_REG_XX_CBYP_TBL_FILL_LVL MCM: XX Tbypass Table is not empty MCM_REG_XX_TBYP_TBL_FILL_LVL MCM: XX Task bypass table is not empty MCM_REG_XX_TBYP_TBL_FILL_LVL MCM: Aggregation Connection FIC buffer is not empty MCM_REG_AGG_CON_FIC_BUF_FILL_LVL MCM: STORM Connection FIC buffer is not empty MCM_REG_SM_CON_FIC_BUF_FILL_LVL MCM: Aggregation Task FIC buffer is not empty MCM_REG_AGG_TASK_FIC_BUF_FILL_LVL MCM: STORM Task FIC buffer is not empty MCM_REG_SM_TASK_FIC_BUF_FILL_LVL MCM: In-process table is not empty MCM_REG_IN_PRCS_TBL_FILL_LVL MCM: CCFC_INIT_CRD is different than reset value MCM: There are pending messages in MCM->CCFC interface MCM_REG_CCFC_INIT_CRD MCM: TCFC_INIT_CRD is different than reset value MCM: There are pending messages in MCM->TCFC interface MCM_REG_TCFC_INIT_CRD MCM: QM_INIT_CRD0 is different than reset value MCM: There are pending messages in MCM->QM interface MCM_REG_QM_INIT_CRD0 MCM: FIC_INIT_CRD is different than reset value MCM: There are pending messages in MCM->MSEM interface MCM_REG_FIC_INIT_CRD MCM: MSDM declared message length unequal to actual MCM_REG_MSDM_LENGTH_MIS MCM: YSDM declared message length unequal to actual MCM_REG_YSDM_LENGTH_MIS MCM: USDM declared message length unequal to actual MCM_REG_USDM_LENGTH_MIS MCM: PBF declared message length unequal to actual MCM_REG_PBF_LENGTH_MIS MCM: TMLD declared message length unequal to actual MCM_REG_TMLD_LENGTH_MIS MCM: QM_P input stage buffer is not empty MCM: There are pending messages in QM(primary)->MCM interface MCM_REG_IS_QM_P_FILL_LVL MCM: QM_S input stage buffer is not empty MCM: There are pending messages in QM(secondary)->MCM interface MCM_REG_IS_QM_S_FILL_LVL MCM: Local STORM input stage buffer is not empty MCM: There are pending messages in MSEM->MCM interface MCM_REG_IS_STORM_FILL_LVL MCM: MSDM input stage buffer is not empty MCM: There are pending messages in MSDM->MCM interface MCM_REG_IS_MSDM_FILL_LVL MCM: YSDM input stage buffer is not empty MCM: There are pending messages in YSDM->MCM interface MCM_REG_IS_YSDM_FILL_LVL MCM: USDM input stage buffer is not empty MCM: There are pending messages in USDM->MCM interface MCM_REG_IS_USDM_FILL_LVL MCM: TMLD input stage buffer is not empty MCM: There are pending messages in TMLD->MCM interface MCM_REG_IS_TMLD_FILL_LVL MCM: USEM input stage buffer is not empty MCM: There are pending messages in USEM->MCM interface MCM_REG_IS_USEM_FILL_LVL MCM: YSEM input stage buffer is not empty MCM: There are pending messages in YSEM->MCM interface MCM_REG_IS_YSEM_FILL_LVL MCM: PBF input stage buffer is not empty MCM: There are pending messages in PBF->MCM interface MCM_REG_IS_PBF_FILL_LVL UCM: Interrupt status 0 is not 0 UCM: There is an interrupt on register 0 UCM_REG_INT_STS_0 UCM: Interrupt status 1 is not 0 UCM: There is an interrupt on register 1 UCM_REG_INT_STS_1 UCM: Parity status 0 is not 0 UCM_REG_PRTY_STS_H_0 UCM: Parity status 1 is not 0 UCM_REG_PRTY_STS_H_1 UCM: Input violation in message first descriptor UCM_REG_FI_DESC_INPUT_VIOLATE UCM: Input violation in message second descriptor UCM_REG_SE_DESC_INPUT_VIOLATE UCM: Aggregation Connection IA part buffer is not empty UCM_REG_IA_AGG_CON_PART_FILL_LVL UCM: STORM Connection IA part buffer is not empty UCM_REG_IA_SM_CON_PART_FILL_LVL UCM: Aggregation Task IA part buffer is not empty UCM_REG_IA_AGG_TASK_PART_FILL_LVL UCM: STORM Task IA part buffer is not empty UCM_REG_IA_SM_TASK_PART_FILL_LVL UCM: Transparent part buffer is not empty UCM_REG_IA_TRANS_PART_FILL_LVL UCM: XX_FREE_CNT is different than reset value UCM: There are messages in the XX RAM UCM_REG_XX_FREE_CNT UCM: XX protection CAM is not empty UCM: XX CAM has active lcids UCM_REG_XX_LCID_CAM_FILL_LVL UCM: there is locked LCID in XX UCM: has locked lcids in xxLock UCM_REG_XX_LOCK_CNT UCM: XX Connection bypass table is not empty UCM_REG_XX_CBYP_TBL_FILL_LVL UCM: XX Task bypass table is not empty UCM_REG_XX_TBYP_TBL_FILL_LVL UCM: XX Tbypass Table is not empty UCM_REG_XX_TBYP_TBL_FILL_LVL UCM: Aggregation Connection FIC buffer is not empty UCM_REG_AGG_CON_FIC_BUF_FILL_LVL UCM: STORM Connection FIC buffer is not empty UCM_REG_SM_CON_FIC_BUF_FILL_LVL UCM: Aggregation Task FIC buffer is not empty UCM_REG_AGG_TASK_FIC_BUF_FILL_LVL UCM: STORM Task FIC buffer is not empty UCM_REG_SM_TASK_FIC_BUF_FILL_LVL UCM: In-process table is not empty UCM_REG_IN_PRCS_TBL_FILL_LVL UCM: CCFC_INIT_CRD is different than reset value UCM: There are pending messages in UCM->CCFC interface UCM_REG_CCFC_INIT_CRD UCM: TCFC_INIT_CRD is different than reset value UCM: There are pending messages in UCM->TCFC interface UCM_REG_TCFC_INIT_CRD UCM: QM_INIT_CRD0 is different than reset value UCM: There are pending messages in UCM->QM interface UCM_REG_QM_INIT_CRD0 UCM: TM_INIT_CRD is different than reset value UCM: There are pending messages in UCM->TM interface UCM_REG_TM_INIT_CRD UCM: FIC_INIT_CRD is different than reset value UCM: There are pending messages in UCM->USEM interface UCM_REG_FIC_INIT_CRD UCM: YSDM declared message length unequal to actual UCM_REG_YSDM_LENGTH_MIS UCM: USDM declared message length unequal to actual UCM_REG_USDM_LENGTH_MIS UCM: DORQ declared message length unequal to actual UCM_REG_DORQ_LENGTH_MIS UCM: PBF declared message length unequal to actual UCM_REG_PBF_LENGTH_MIS UCM: RDIF declared message length unequal to actual UCM_REG_RDIF_LENGTH_MIS UCM: TDIF declared message length unequal to actual UCM_REG_TDIF_LENGTH_MIS UCM: MULD declared message length unequal to actual UCM_REG_MULD_LENGTH_MIS UCM: YULD declared message length unequal to actual UCM_REG_YULD_LENGTH_MIS UCM: QM_P input stage buffer is not empty UCM: There are pending messages in QM(primary)->UCM interface UCM_REG_IS_QM_P_FILL_LVL UCM: QM_S input stage buffer is not empty UCM: There are pending messages in QM(secondary)->UCM interface UCM_REG_IS_QM_S_FILL_LVL UCM: TM input stage buffer is not empty UCM: There are pending messages in TM->UCM interface UCM_REG_IS_TM_FILL_LVL UCM: Local STORM input stage buffer is not empty UCM: There are pending messages in USEM->UCM interface UCM_REG_IS_STORM_FILL_LVL UCM: YSDM input stage buffer is not empty UCM: There are pending messages in YSDM->UCM interface UCM_REG_IS_YSDM_FILL_LVL UCM: USDM input stage buffer is not empty UCM: There are pending messages in USDM->UCM interface UCM_REG_IS_USDM_FILL_LVL UCM: RDIF input stage buffer is not empty UCM: There are pending messages in RDIF->UCM interface UCM_REG_IS_RDIF_FILL_LVL UCM: TDIF input stage buffer is not empty UCM: There are pending messages in TDIF->UCM interface UCM_REG_IS_TDIF_FILL_LVL UCM: MULD input stage buffer is not empty UCM: There are pending messages in MULD->UCM interface UCM_REG_IS_MULD_FILL_LVL UCM: YULD input stage buffer is not empty UCM: There are pending messages in YULD->UCM interface UCM_REG_IS_YULD_FILL_LVL UCM: DORQ input stage buffer is not empty UCM: There are pending messages in DORQ->UCM interface UCM_REG_IS_DORQ_FILL_LVL UCM: PBF input stage buffer is not empty UCM: There are pending messages in PBF->UCM interface UCM_REG_IS_PBF_FILL_LVL XSEM: interrupt status 0 is not 0 XSEM: Fatal XSEM error XSEM_REG_INT_STS_0 XSEM: interrupt status 1 is not 0 XSEM: Fatal XSEM error XSEM_REG_INT_STS_1 XSEM: SEM FAST Parity status is not 0 XSEM_REG_PRTY_STS XSEM: Parity status is not 0 XSEM_REG_PRTY_STS_H_0 XSEM: PF error vector is not zero XSEM: Error was returned for one or more PF/s XSEM_REG_PF_ERR_VECTOR XSEM: FOC1 credit is not full XSEM: Not all credits from XY-Loader interface were returned XSEM_REG_FOC_CREDIT XSEM: FOC0 credit is not full XSEM: Not all credits from XCM interface were returned XSEM_REG_FOC_CREDIT XSEM: Thread error vector is not zero XSEM: There are threads with 'thread error' bit set XSEM_REG_THREAD_ERROR XSEM: Some threads are ready XSEM: There are threads with 'thread ready' bit set XSEM_REG_THREAD_RDY XSEM: some threads are valid XSEM: There are valid threads sleeping in the passive buffer XSEM_REG_THREAD_VALID XSEM: DRA is not empty XSEM: There is data to DRA on the FOC interface XSEM_REG_DRA_EMPTY XSEM: External passive is not empty XSEM: The FIFO which stores request from SDM to passive buffer is not empty XSEM_REG_EXT_PAS_EMPTY XSEM: FIC is not empty XSEM: FIC FIFO is not empty XSEM_REG_FIC_EMPTY XSEM: Slow dbg fifo is not empty XSEM: The debug FIFO is not empty XSEM_REG_SLOW_DBG_EMPTY XSEM: Slow dra fin fifo is not empty XSEM: There are outstanding FIN requests in the FIN FIFO XSEM_REG_SLOW_DRA_FIN_EMPTY XSEM: Slow dra read fifo is not empty XSEM: DRA read FIFO is not empty XSEM_REG_SLOW_DRA_RD_EMPTY XSEM: Slow dra write fifo is not empty XSEM: DRA write FIFO is not empty XSEM_REG_SLOW_DRA_WR_EMPTY XSEM: Slow ext store fifo is not empty XSEM: External store FIFO is not empty XSEM_REG_SLOW_EXT_STORE_EMPTY XSEM: Slow ext load fifo is not empty XSEM: External load FIFO is not empty XSEM_REG_SLOW_EXT_LOAD_EMPTY XSEM: Slow ram read fifo is not empty XSEM: RAM read FIFO is not empty XSEM_REG_SLOW_RAM_RD_EMPTY XSEM: Slow ram write fifo is not empty XSEM: RAM write FIFO is not empty XSEM_REG_SLOW_RAM_WR_EMPTY XSEM: SYNC DBG fifo is not empty XSEM: The debug FIFO is not empty XSEM_REG_SYNC_DBG_EMPTY XSEM: Thread fifo is not empty XSEM: The thread FIFO is not empty XSEM_REG_THREAD_FIFO_EMPTY XSEM: External store IF is full XSDM: FULL from XSDM on external store interface is asserted XSEM_REG_EXT_STORE_IF_FULL XSEM: Passive IF is full XSEM: FULL to XSDM on passive buffer interface is asserted XSEM_REG_PAS_IF_FULL XSEM: RAM IF is full XSEM: FULL to XSDM on RAM R/W interface is asserted XSEM_REG_RAM_IF_FULL XSEM: Thread overrun vector is not zero XSEM: There are threads which are active for more than a pre-defined interval XSEM_REG_THREAD_ORUN_NUM XSEM: DBG IF is full XSDM: FULL from DBG is asserted XSEM_REG_DBG_IF_FULL YSEM: interrupt status 0 is not 0 YSEM: Fatal YSEM error YSEM_REG_INT_STS_0 YSEM: interrupt status 1 is not 0 YSEM: Fatal YSEM error YSEM_REG_INT_STS_1 YSEM: SEM FAST Parity status is not 0 YSEM_REG_PRTY_STS YSEM: Parity status is not 0 YSEM_REG_PRTY_STS_H_0 YSEM: PF error vector is not zero YSEM: Error was returned for one or more PF/s YSEM_REG_PF_ERR_VECTOR YSEM: FOC3 credit is not full YSEM: Not all credits from XCM interface were returned YSEM_REG_FOC_CREDIT YSEM: FOC4 credit is not full YSEM: Not all credits from YCM interface were returned YSEM_REG_FOC_CREDIT YSEM: FOC5 credit is not full YSEM: Not all credits from PBF interface were returned YSEM_REG_FOC_CREDIT YSEM: FOC2 credit is not full YSEM: Not all credits from YU-Loader interface were returned YSEM_REG_FOC_CREDIT YSEM: FOC0 credit is not full YSEM: Not all credits from TCM interface were returned YSEM_REG_FOC_CREDIT YSEM: FOC1 credit is not full YSEM: Not all credits from MCM interface were returned YSEM_REG_FOC_CREDIT YSEM: Thread error vector is not zero YSEM: There are threads with 'thread error' bit set YSEM_REG_THREAD_ERROR YSEM: Some threads are ready YSEM: There are threads with 'thread ready' bit set YSEM_REG_THREAD_RDY YSEM: some threads are valid YSEM: There are valid threads sleeping in the passive buffer YSEM_REG_THREAD_VALID YSEM: DRA is not empty YSEM: There is data to DRA on the FOC interface YSEM_REG_DRA_EMPTY YSEM: External passive is not empty YSEM: The FIFO which stores request from SDM to passive buffer is not empty YSEM_REG_EXT_PAS_EMPTY YSEM: FIC is not empty YSEM: FIC FIFO is not empty YSEM_REG_FIC_EMPTY YSEM: Slow dbg fifo is not empty YSEM: The debug FIFO is not empty YSEM_REG_SLOW_DBG_EMPTY YSEM: Slow dra fin fifo is not empty YSEM: There are outstanding FIN requests in the FIN FIFO YSEM_REG_SLOW_DRA_FIN_EMPTY YSEM: Slow dra read fifo is not empty YSEM: DRA read FIFO is not empty YSEM_REG_SLOW_DRA_RD_EMPTY YSEM: Slow dra write fifo is not empty YSEM: DRA write FIFO is not empty YSEM_REG_SLOW_DRA_WR_EMPTY YSEM: Slow ext store fifo is not empty YSEM: External store FIFO is not empty YSEM_REG_SLOW_EXT_STORE_EMPTY YSEM: Slow ext load fifo is not empty YSEM: External load FIFO is not empty YSEM_REG_SLOW_EXT_LOAD_EMPTY YSEM: Slow ram read fifo is not empty YSEM: RAM read FIFO is not empty YSEM_REG_SLOW_RAM_RD_EMPTY YSEM: Slow ram write fifo is not empty YSEM: RAM write FIFO is not empty YSEM_REG_SLOW_RAM_WR_EMPTY YSEM: SYNC DBG fifo is not empty YSEM: The debug FIFO is not empty YSEM_REG_SYNC_DBG_EMPTY YSEM: Thread fifo is not empty YSEM: The thread FIFO is not empty YSEM_REG_THREAD_FIFO_EMPTY YSEM: External store IF is full YSDM: FULL from YSDM on external store interface is asserted YSEM_REG_EXT_STORE_IF_FULL YSEM: Passive IF is full YSEM: FULL to YSDM on passive buffer interface is asserted YSEM_REG_PAS_IF_FULL YSEM: RAM IF is full YSEM: FULL to YSDM on RAM R/W interface is asserted YSEM_REG_RAM_IF_FULL YSEM: Thread overrun vector is not zero YSEM: There are threads which are active for more than a pre-defined interval YSEM_REG_THREAD_ORUN_NUM YSEM: DBG IF is full YSDM: FULL from DBG is asserted YSEM_REG_DBG_IF_FULL PSEM: interrupt status 0 is not 0 PSEM: Fatal PSEM error PSEM_REG_INT_STS_0 PSEM: interrupt status 1 is not 0 PSEM: Fatal PSEM error PSEM_REG_INT_STS_1 PSEM: SEM FAST Parity status is not 0 PSEM_REG_PRTY_STS PSEM: Parity status is not 0 PSEM_REG_PRTY_STS_H_0 PSEM: PF error vector is not zero PSEM: Error was returned for one or more PF/s PSEM_REG_PF_ERR_VECTOR PSEM: FOC1 credit is not full PSEM: Not all credits from PBF interface were returned PSEM_REG_FOC_CREDIT PSEM: FOC0 credit is not full PSEM: Not all credits from PCM interface were returned PSEM_REG_FOC_CREDIT PSEM: Thread error vector is not zero PSEM: There are threads with 'thread error' bit set PSEM_REG_THREAD_ERROR PSEM: Some threads are ready PSEM: There are threads with 'thread ready' bit set PSEM_REG_THREAD_RDY PSEM: some threads are valid PSEM: There are valid threads sleeping in the passive buffer PSEM_REG_THREAD_VALID PSEM: DRA is not empty PSEM: There is data to DRA on the FOC interface PSEM_REG_DRA_EMPTY PSEM: External passive is not empty PSEM: The FIFO which stores request from SDM to passive buffer is not empty PSEM_REG_EXT_PAS_EMPTY PSEM: FIC is not empty PSEM: FIC FIFO is not empty PSEM_REG_FIC_EMPTY PSEM: Slow dbg fifo is not empty PSEM: The debug FIFO is not empty PSEM_REG_SLOW_DBG_EMPTY PSEM: Slow dra fin fifo is not empty PSEM: There are outstanding FIN requests in the FIN FIFO PSEM_REG_SLOW_DRA_FIN_EMPTY PSEM: Slow dra read fifo is not empty PSEM: DRA read FIFO is not empty PSEM_REG_SLOW_DRA_RD_EMPTY PSEM: Slow dra write fifo is not empty PSEM: DRA write FIFO is not empty PSEM_REG_SLOW_DRA_WR_EMPTY PSEM: Slow ext store fifo is not empty PSEM: External store FIFO is not empty PSEM_REG_SLOW_EXT_STORE_EMPTY PSEM: Slow ext load fifo is not empty PSEM: External load FIFO is not empty PSEM_REG_SLOW_EXT_LOAD_EMPTY PSEM: Slow ram read fifo is not empty PSEM: RAM read FIFO is not empty PSEM_REG_SLOW_RAM_RD_EMPTY PSEM: Slow ram write fifo is not empty PSEM: RAM write FIFO is not empty PSEM_REG_SLOW_RAM_WR_EMPTY PSEM: SYNC DBG fifo is not empty PSEM: The debug FIFO is not empty PSEM_REG_SYNC_DBG_EMPTY PSEM: Thread fifo is not empty PSEM: The thread FIFO is not empty PSEM_REG_THREAD_FIFO_EMPTY PSEM: External store IF is full PSDM: FULL from PSDM on external store interface is asserted PSEM_REG_EXT_STORE_IF_FULL PSEM: Passive IF is full PSEM: FULL to PSDM on passive buffer interface is asserted PSEM_REG_PAS_IF_FULL PSEM: RAM IF is full PSEM: FULL to PSDM on RAM R/W interface is asserted PSEM_REG_RAM_IF_FULL PSEM: Thread overrun vector is not zero PSEM: There are threads which are active for more than a pre-defined interval PSEM_REG_THREAD_ORUN_NUM PSEM: DBG IF is full PSDM: FULL from DBG is asserted PSEM_REG_DBG_IF_FULL TSEM: interrupt status 0 is not 0 TSEM: Fatal TSEM error TSEM_REG_INT_STS_0 TSEM: interrupt status 1 is not 0 TSEM: Fatal TSEM error TSEM_REG_INT_STS_1 TSEM: SEM FAST Parity status is not 0 TSEM_REG_PRTY_STS TSEM: Parity status is not 0 TSEM_REG_PRTY_STS_H_0 TSEM: PF error vector is not zero TSEM: Error was returned for one or more PF/s TSEM_REG_PF_ERR_VECTOR TSEM: FOC1 credit is not full TSEM: Not all credits from TM-Loader interface were returned TSEM_REG_FOC_CREDIT TSEM: FOC0 credit is not full TSEM: Not all credits from TCM interface were returned TSEM_REG_FOC_CREDIT TSEM: Thread error vector is not zero TSEM: There are threads with 'thread error' bit set TSEM_REG_THREAD_ERROR TSEM: Some threads are ready TSEM: There are threads with 'thread ready' bit set TSEM_REG_THREAD_RDY TSEM: some threads are valid TSEM: There are valid threads sleeping in the passive buffer TSEM_REG_THREAD_VALID TSEM: DRA is not empty TSEM: There is data to DRA on the FOC interface TSEM_REG_DRA_EMPTY TSEM: External passive is not empty TSEM: The FIFO which stores request from SDM to passive buffer is not empty TSEM_REG_EXT_PAS_EMPTY TSEM: FIC is not empty TSEM: FIC FIFO is not empty TSEM_REG_FIC_EMPTY TSEM: Slow dbg fifo is not empty TSEM: The debug FIFO is not empty TSEM_REG_SLOW_DBG_EMPTY TSEM: Slow dra fin fifo is not empty TSEM: There are outstanding FIN requests in the FIN FIFO TSEM_REG_SLOW_DRA_FIN_EMPTY TSEM: Slow dra read fifo is not empty TSEM: DRA read FIFO is not empty TSEM_REG_SLOW_DRA_RD_EMPTY TSEM: Slow dra write fifo is not empty TSEM: DRA write FIFO is not empty TSEM_REG_SLOW_DRA_WR_EMPTY TSEM: Slow ext store fifo is not empty TSEM: External store FIFO is not empty TSEM_REG_SLOW_EXT_STORE_EMPTY TSEM: Slow ext load fifo is not empty TSEM: External load FIFO is not empty TSEM_REG_SLOW_EXT_LOAD_EMPTY TSEM: Slow ram read fifo is not empty TSEM: RAM read FIFO is not empty TSEM_REG_SLOW_RAM_RD_EMPTY TSEM: Slow ram write fifo is not empty TSEM: RAM write FIFO is not empty TSEM_REG_SLOW_RAM_WR_EMPTY TSEM: SYNC DBG fifo is not empty TSEM: The debug FIFO is not empty TSEM_REG_SYNC_DBG_EMPTY TSEM: Thread fifo is not empty TSEM: The thread FIFO is not empty TSEM_REG_THREAD_FIFO_EMPTY TSEM: External store IF is full TSDM: FULL from TSDM on external store interface is asserted TSEM_REG_EXT_STORE_IF_FULL TSEM: Passive IF is full TSEM: FULL to TSDM on passive buffer interface is asserted TSEM_REG_PAS_IF_FULL TSEM: RAM IF is full TSEM: FULL to TSDM on RAM R/W interface is asserted TSEM_REG_RAM_IF_FULL TSEM: Thread overrun vector is not zero TSEM: There are threads which are active for more than a pre-defined interval TSEM_REG_THREAD_ORUN_NUM TSEM: DBG IF is full TSDM: FULL from DBG is asserted TSEM_REG_DBG_IF_FULL MSEM: interrupt status 0 is not 0 MSEM: Fatal MSEM error MSEM_REG_INT_STS_0 MSEM: interrupt status 1 is not 0 MSEM: Fatal MSEM error MSEM_REG_INT_STS_1 MSEM: SEM FAST Parity status is not 0 MSEM_REG_PRTY_STS MSEM: Parity status is not 0 MSEM_REG_PRTY_STS_H_0 MSEM: PF error vector is not zero MSEM: Error was returned for one or more PF/s MSEM_REG_PF_ERR_VECTOR MSEM: FOC4 credit is not full MSEM: Not all credits from YCM interface were returned MSEM_REG_FOC_CREDIT MSEM: FOC3 credit is not full MSEM: Not all credits from XCM interface were returned MSEM_REG_FOC_CREDIT MSEM: FOC2 credit is not full MSEM: Not all credits from MU-Loader interface were returned MSEM_REG_FOC_CREDIT MSEM: FOC1 credit is not full MSEM: Not all credits from MCM interface were returned MSEM_REG_FOC_CREDIT MSEM: FOC0 credit is not full MSEM: Not all credits from TCM interface were returned MSEM_REG_FOC_CREDIT MSEM: FOC5 credit is not full MSEM: Not all credits from PRM interface were returned MSEM_REG_FOC_CREDIT MSEM: Thread error vector is not zero MSEM: There are threads with 'thread error' bit set MSEM_REG_THREAD_ERROR MSEM: Some threads are ready MSEM: There are threads with 'thread ready' bit set MSEM_REG_THREAD_RDY MSEM: some threads are valid MSEM: There are valid threads sleeping in the passive buffer MSEM_REG_THREAD_VALID MSEM: DRA is not empty MSEM: There is data to DRA on the FOC interface MSEM_REG_DRA_EMPTY MSEM: External passive is not empty MSEM: The FIFO which stores request from SDM to passive buffer is not empty MSEM_REG_EXT_PAS_EMPTY MSEM: FIC is not empty MSEM: FIC FIFO is not empty MSEM_REG_FIC_EMPTY MSEM: Slow dbg fifo is not empty MSEM: The debug FIFO is not empty MSEM_REG_SLOW_DBG_EMPTY MSEM: Slow dra fin fifo is not empty MSEM: There are outstanding FIN requests in the FIN FIFO MSEM_REG_SLOW_DRA_FIN_EMPTY MSEM: Slow dra read fifo is not empty MSEM: DRA read FIFO is not empty MSEM_REG_SLOW_DRA_RD_EMPTY MSEM: Slow dra write fifo is not empty MSEM: DRA write FIFO is not empty MSEM_REG_SLOW_DRA_WR_EMPTY MSEM: Slow ext store fifo is not empty MSEM: External store FIFO is not empty MSEM_REG_SLOW_EXT_STORE_EMPTY MSEM: Slow ext load fifo is not empty MSEM: External load FIFO is not empty MSEM_REG_SLOW_EXT_LOAD_EMPTY MSEM: Slow ram read fifo is not empty MSEM: RAM read FIFO is not empty MSEM_REG_SLOW_RAM_RD_EMPTY MSEM: Slow ram write fifo is not empty MSEM: RAM write FIFO is not empty MSEM_REG_SLOW_RAM_WR_EMPTY MSEM: SYNC DBG fifo is not empty MSEM: The debug FIFO is not empty MSEM_REG_SYNC_DBG_EMPTY MSEM: Thread fifo is not empty MSEM: The thread FIFO is not empty MSEM_REG_THREAD_FIFO_EMPTY MSEM: External store IF is full MSDM: FULL from MSDM on external store interface is asserted MSEM_REG_EXT_STORE_IF_FULL MSEM: Passive IF is full MSEM: FULL to MSDM on passive buffer interface is asserted MSEM_REG_PAS_IF_FULL MSEM: RAM IF is full MSEM: FULL to MSDM on RAM R/W interface is asserted MSEM_REG_RAM_IF_FULL MSEM: Thread overrun vector is not zero MSEM: There are threads which are active for more than a pre-defined interval MSEM_REG_THREAD_ORUN_NUM MSEM: DBG IF is full MSDM: FULL from DBG is asserted MSEM_REG_DBG_IF_FULL USEM: interrupt status 0 is not 0 USEM: Fatal USEM error USEM_REG_INT_STS_0 USEM: interrupt status 1 is not 0 USEM: Fatal USEM error USEM_REG_INT_STS_1 USEM: SEM FAST Parity status is not 0 USEM_REG_PRTY_STS USEM: Parity status is not 0 USEM_REG_PRTY_STS_H_0 USEM: PF error vector is not zero USEM: Error was returned for one or more PF/s USEM_REG_PF_ERR_VECTOR USEM: FOC2 credit is not full USEM: Not all credits from XCM interface were returned USEM_REG_FOC_CREDIT USEM: FOC3 credit is not full USEM: Not all credits from YCM interface were returned USEM_REG_FOC_CREDIT USEM: FOC4 credit is not full USEM: Not all credits from PRM interface were returned USEM_REG_FOC_CREDIT USEM: FOC0 credit is not full USEM: Not all credits from MCM interface were returned USEM_REG_FOC_CREDIT USEM: FOC1 credit is not full USEM: Not all credits from UCM interface were returned USEM_REG_FOC_CREDIT USEM: Thread error vector is not zero USEM: There are threads with 'thread error' bit set USEM_REG_THREAD_ERROR USEM: Some threads are ready USEM: There are threads with 'thread ready' bit set USEM_REG_THREAD_RDY USEM: some threads are valid USEM: There are valid threads sleeping in the passive buffer USEM_REG_THREAD_VALID USEM: DRA is not empty USEM: There is data to DRA on the FOC interface USEM_REG_DRA_EMPTY USEM: External passive is not empty USEM: The FIFO which stores request from SDM to passive buffer is not empty USEM_REG_EXT_PAS_EMPTY USEM: FIC is not empty USEM: FIC FIFO is not empty USEM_REG_FIC_EMPTY USEM: Slow dbg fifo is not empty USEM: The debug FIFO is not empty USEM_REG_SLOW_DBG_EMPTY USEM: Slow dra fin fifo is not empty USEM: There are outstanding FIN requests in the FIN FIFO USEM_REG_SLOW_DRA_FIN_EMPTY USEM: Slow dra read fifo is not empty USEM: DRA read FIFO is not empty USEM_REG_SLOW_DRA_RD_EMPTY USEM: Slow dra write fifo is not empty USEM: DRA write FIFO is not empty USEM_REG_SLOW_DRA_WR_EMPTY USEM: Slow ext store fifo is not empty USEM: External store FIFO is not empty USEM_REG_SLOW_EXT_STORE_EMPTY USEM: Slow ext load fifo is not empty USEM: External load FIFO is not empty USEM_REG_SLOW_EXT_LOAD_EMPTY USEM: Slow ram read fifo is not empty USEM: RAM read FIFO is not empty USEM_REG_SLOW_RAM_RD_EMPTY USEM: Slow ram write fifo is not empty USEM: RAM write FIFO is not empty USEM_REG_SLOW_RAM_WR_EMPTY USEM: SYNC DBG fifo is not empty USEM: The debug FIFO is not empty USEM_REG_SYNC_DBG_EMPTY USEM: Thread fifo is not empty USEM: The thread FIFO is not empty USEM_REG_THREAD_FIFO_EMPTY USEM: External store IF is full USDM: FULL from USDM on external store interface is asserted USEM_REG_EXT_STORE_IF_FULL USEM: Passive IF is full USEM: FULL to USDM on passive buffer interface is asserted USEM_REG_PAS_IF_FULL USEM: RAM IF is full USEM: FULL to USDM on RAM R/W interface is asserted USEM_REG_RAM_IF_FULL USEM: Thread overrun vector is not zero USEM: There are threads which are active for more than a pre-defined interval USEM_REG_THREAD_ORUN_NUM USEM: DBG IF is full USDM: FULL from DBG is asserted USEM_REG_DBG_IF_FULL PCIE: Parity status is not 0 PCIE_REG_PRTY_STS_H_0 IGU: block is not in idle. There are pending MSI/MSIX messages IGU_REG_PENDING_BITS_STATUS IGU MSI/MSIX message write done pending is not empty IGU: MSI/MSIX write done pending IGU_REG_WRITE_DONE_PENDING CNIG: Interrupt detected CNIG: Interrupt detected CNIG_REG_INT_STS CNIG_REG_CNIG_DBG_FIFO_ERROR CNIG:Parity error detected. CNIG_REG_PRTY_STS PSWHST: Access to disabled VF took place. (0) - 0 - read 1 - write. (4:1) - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE). (5) vf_valid. (12:6) vfid. (15:13) pfid. PSWHST_REG_VF_DISABLED_ERROR_VALID PSWHST_REG_VF_DISABLED_ERROR_DATA PGL: FLR request is set for VF addresses 223-192 PGLUE_B_REG_FLR_REQUEST_VF_223_192 PGL: FLR request is set for VF addresses 255-224 PGLUE_B_REG_FLR_REQUEST_VF_255_224 PGLUE_B: Packet received from PCIe not according to the rules. PGLUE_B_REG_INCORRECT_RCV_DETAILS PGLUE_B: was_error for VFs 192-223 is not 0 PGLUE_B_REG_WAS_ERROR_VF_223_192 PGLUE_B: was_error for VFs 224-255 is not 0 PGLUE_B_REG_WAS_ERROR_VF_255_224 PGLUE_B: There are outstanding read requests for tags 128-159. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_159_128 PGLUE_B: There are outstanding read requests for tags 160-191. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_191_160 PGLUE_B: There are outstanding read requests for tags 192-223. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_223_192 PGLUE_B: There are outstanding read requests for tags 224-255. Not all completions have arrived for read requests on tags that are marked with 0 PGLUE_B_REG_TAGS_255_224 QM: Other PQ-s pointer table - read and write variables not equal for 128 other queues QM: There are pending tasks in other queues QM_REG_PTRTBLOTHER QM: Other PQ-s pointer table - read and write variables not equal QM: There are pending tasks in other queues QM_REG_PTRTBLOTHER QM: QSTATUSTX reg is not 0. QM_REG_QSTATUSTX_0 QM: QSTATUSOTHER reg is not 0. QM_REG_QSTATUSOTHER_0 QM: VOQ line credit is not equal to init credit QM: VOQ line credit is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ line credit is not equal to init credit QM: VOQ line credit on NW queues is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ line credit is not equal to init credit QM: VOQ line credit on LB queues is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit on LB queues is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit on NW queues is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: TX PQ-s pointer table - read and write variables not equal QM: There are pending tasks in tx queues QM_REG_PTRTBLTX QM: TX PQ-s pointer table - read and write variables not equal for 512 queues QM: There are pending tasks in tx queues QM_REG_PTRTBLTX BRB: Write client FIFOs are not empty (value != 0x1ffe) BRB: Write client FIFOs are not empty (value != 0x1ffe) BRB_REG_WC_EMPTY_0 BRB: Read EOP clients FIFOs are not empty BRB: Read EOP clients FIFOs are not empty BRB_REG_RC_EOP_EMPTY BRB: Write client status is not 0 BRB: Write client status is not 0 BRB_REG_WC_STATUS_0 NIG: Data path parity error occurred. NIG: Data path parity error occurred. NIG_REG_PRTY_STS NIG_REG_RX_PARITY_ERR NIG_REG_TX_PARITY_ERR NIG_REG_LB_PARITY_ERR BTB: Interrupt status 0 is set BTB: Fatal BTB error BTB_REG_INT_STS_0 BTB_REG_STOPPED_RD_REQ BTB_REG_STOPPED_RLS_REQ BTB: Interrupt status 4 is set BTB: Fatal BTB error BTB_REG_INT_STS_4 BTB_REG_STOPPED_RD_REQ BTB_REG_STOPPED_RLS_REQ XCM: QM Active State Counter is not 0 XCM_REG_QM_ACT_ST_CNT XSEM: VF error vector is not zero XSEM: Error was returned for one or more VF/s XSEM_REG_VF_ERR_VECTOR YSEM: VF error vector is not zero YSEM: Error was returned for one or more VF/s YSEM_REG_VF_ERR_VECTOR PSEM: VF error vector is not zero PSEM: Error was returned for one or more VF/s PSEM_REG_VF_ERR_VECTOR TSEM: VF error vector is not zero TSEM: Error was returned for one or more VF/s TSEM_REG_VF_ERR_VECTOR MSEM: VF error vector is not zero MSEM: Error was returned for one or more VF/s MSEM_REG_VF_ERR_VECTOR USEM: VF error vector is not zero USEM: Error was returned for one or more VF/s USEM_REG_VF_ERR_VECTOR PCIE: Parity status is not 0 PCIE_REG_PRTY_STS_H_0 PSWHST: Access to disabled VF took place. (0) - 0 - read 1 - write. (4:1) - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE). (5) vf_valid. (13:6) vfid. (17:14) pfid. PSWHST_REG_VF_DISABLED_ERROR_VALID PSWHST_REG_VF_DISABLED_ERROR_DATA QM: QSTATUSTX reg is not 0. QM_REG_QSTATUSTX_0 QM: QSTATUSOTHER reg is not 0. QM_REG_QSTATUSOTHER_0 BRB: Write client FIFOs are not empty (value != 0x1ffe) BRB: Write client FIFOs are not empty (value != 0x1ffe) BRB_REG_WC_EMPTY_0 BRB: Write client status is not 0 BRB: Write client status is not 0 BRB_REG_WC_STATUS_0 PSWRQ2: SR_CNT_per_vq7 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_7 PSWRQ2_REG_MAX_SRS_VQ7 PSWRQ2: SR_CNT_per_vq8 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_8 PSWRQ2_REG_MAX_SRS_VQ8 PSWRQ2: SR_CNT_per_vq10 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_10 PSWRQ2_REG_MAX_SRS_VQ10 PSWRQ2: SR_CNT_per_vq13 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_13 PSWRQ2_REG_MAX_SRS_VQ13 PSWRQ2: SR_CNT_per_vq14 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_14 PSWRQ2_REG_MAX_SRS_VQ14 PSWRQ2: SR_CNT_per_vq20 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_20 PSWRQ2_REG_MAX_SRS_VQ20 PSWRQ2: SR_CNT_per_vq25 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_25 PSWRQ2_REG_MAX_SRS_VQ25 PSWRQ2: SR_CNT_per_vq27 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_27 PSWRQ2_REG_MAX_SRS_VQ27 PSWRQ2: SR_CNT_per_vq31 is not equal to MAX_SRS_vq PSWRQ2_REG_SR_CNT_PER_VQ_31 PSWRQ2_REG_MAX_SRS_VQ31 PSWRQ2: blk_cnt_per_vq7 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_7 PSWRQ2_REG_MAX_BLKS_VQ7 PSWRQ2: blk_cnt_per_vq8 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_8 PSWRQ2_REG_MAX_BLKS_VQ8 PSWRQ2: blk_cnt_per_vq10 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_10 PSWRQ2_REG_MAX_BLKS_VQ10 PSWRQ2: blk_cnt_per_vq13 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_13 PSWRQ2_REG_MAX_BLKS_VQ13 PSWRQ2: blk_cnt_per_vq14 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_14 PSWRQ2_REG_MAX_BLKS_VQ14 PSWRQ2: blk_cnt_per_vq20 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_20 PSWRQ2_REG_MAX_BLKS_VQ20 PSWRQ2: blk_cnt_per_vq25 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_25 PSWRQ2_REG_MAX_BLKS_VQ25 PSWRQ2: blk_cnt_per_vq27 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_27 PSWRQ2_REG_MAX_BLKS_VQ27 PSWRQ2: blk_cnt_per_vq31 is not equal to max_blks_vq PSWRQ2_REG_BLK_CNT_PER_VQ_31 PSWRQ2_REG_MAX_BLKS_VQ31 TM: TM_REG_INT_STS_1 bits 9,8,7,6,5,0 are set, one of cload_res_loadcancel_task, cload_res_loaderr_task, pxp_rd_data_eop_error, pend_task_scan, pend_conn_scan, cload_res_loadcancel_conn attentions is asserted TM: There is an interrupt on bits of register 1 TM_REG_INT_STS_1 BMB: Parity status 0 is not 0 BMB_REG_PRTY_STS_H_0 BMB: Parity status 1 is not 0 BMB_REG_PRTY_STS_H_1 TM: TM_REG_INT_STS_1 bits 9,8,7,0 are set, one of cload_res_loadcancel_task, cload_res_loaderr_task, pxp_rd_data_eop_error, cload_res_loadcancel_conn attentions is asserted TM: There is an interrupt on bits of register 1 TM_REG_INT_STS_1 PCIE: ucorr_err_status is not 0 PGLCS_REG_PGL_CS_UNCORR_ERR_STATUS_OFF PCIE: ucorr_err_status - Flow Control Protocol Error PGLCS_REG_PGL_CS_UNCORR_ERR_STATUS_OFF PCIE: ucorr_err_status - Unsupported request error PGLCS_REG_PGL_CS_UNCORR_ERR_STATUS_OFF PCIE: error packet header is not 0 PGLCS_REG_PGL_CS_HDR_LOG_0_OFF PGL: Underflow in TX sync FIFO. Bit0: TX completion FIFO. Bit1: TXR header FIFO. Bit2: TXW header FIFO. Bit3: TXW data FIFO. PGL: Underflow in TX sync FIFO PGLCS_REG_SYNCFIFO_POP_UNDERFLOW PGL: Overflow in RX sync FIFO. Bit0: RX NP FIFO. Bit1: RX posted header FIFO. Bits 5:2: RX posted data FIFOs. PGL: Overflow in RX sync FIFO PGLCS_REG_SYNCFIFO_PUSH_OVERFLOW PGL: There are entries in TX sync FIFOs. Bits 4:0: TX completion FIFO. Bits 9:5: TXR header FIFO. Bit14:10: TXW header FIFO. Bit19:14: TXW data FIFO. PGL: There are entries in TX sync FIFOs PGLCS_REG_TX_SYNCFIFO_POP_STATUS PCIE: HW status & 0xE001 is not 0 PCIE_REG_INT_STS IGU: block is not in idle. There are pending MSI/MSIX messages IGU_REG_PENDING_BITS_STATUS IGU MSI/MSIX message write done pending is not empty IGU: MSI/MSIX write done pending IGU_REG_WRITE_DONE_PENDING CNIG: Interrupt detected CNIG: Interrupt detected CNIG_REG_INT_STS CNIG_REG_CNIG_DBG_FIFO_ERROR CNIG:Parity error detected. CNIG_REG_PRTY_STS PGL: Overflow in TX sync FIFO. Bit0: TX completion FIFO. Bit1: TXR header FIFO. Bit2: TXW header FIFO. Bit3: TXW data FIFO. PGL: Overflow in TX sync FIFO PGLUE_B_REG_SYNCFIFO_PUSH_OVERFLOW PGL: Underflow in RX sync FIFO. Bit0: RX NP FIFO. Bit1: RX posted header FIFO. Bits 5:2: RX posted data FIFOs. PGL: Underflow in RX sync FIFO PGLUE_B_REG_SYNCFIFO_POP_UNDERFLOW PGL: There are entries in RX sync FIFOs. Bits 8:0: RX NP FIFO. Bits 17:9: RX posted header FIFO. PGL: There are entries in RX sync FIFOs PGLUE_B_REG_RXH_SYNCFIFO_POP_STATUS PGL: There are entries in RX sync FIFOs. Bits 6:0: RX posted data FIFO 0. Bits 13:7: RX posted data FIFO 1. Bits 20:14: RX posted data FIFO 2. Bits 27:21: RX posted data FIFO 3. PGL: There are entries in RX sync FIFOs PGLUE_B_REG_RXD_SYNCFIFO_POP_STATUS PGLUE_B_REG_RXH_SYNCFIFO_POP_STATUS QM: Other PQ-s pointer table - read and write variables not equal QM: There are pending tasks in other queues QM_REG_PTRTBLOTHER QM: Other PQ-s pointer table - read and write variables not equal for 128 other queues QM: There are pending tasks in other queues QM_REG_PTRTBLOTHER QM: VOQ line credit is not equal to init credit QM: VOQ line credit on NW queues is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ line credit is not equal to init credit QM: VOQ line credit on LB queues is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ line credit is not equal to init credit QM: VOQ line credit is not equal to init credit QM_REG_VOQCRDLINE QM_REG_VOQINITCRDLINE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit on LB queues is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: VOQ byte credit is not equal to init credit QM: VOQ byte credit on NW queues is not equal to init credit QM_REG_VOQCRDBYTE QM_REG_VOQINITCRDBYTE MISC_REG_PORT_MODE QM: TX PQ-s pointer table - read and write variables not equal for 512 queues QM: There are pending tasks in tx queues QM_REG_PTRTBLTX QM: TX PQ-s pointer table - read and write variables not equal QM: There are pending tasks in tx queues QM_REG_PTRTBLTX BRB: Read EOP clients FIFOs are not empty BRB: Read EOP clients FIFOs are not empty BRB_REG_RC_EOP_EMPTY TC 0 in MAC 2 occupancy is not 0x0 There are packets in BRB belonging to MAC 2 traffic-class 0 BRB_REG_MAC2_TC_OCCUPANCY_0 TC 1 in MAC 2 occupancy is not 0x0 There are packets in BRB belonging to MAC 2 traffic-class 1 BRB_REG_MAC2_TC_OCCUPANCY_1 TC 2 in MAC 2 occupancy is not 0x0 There are packets in BRB belonging to MAC 2 traffic-class 2 BRB_REG_MAC2_TC_OCCUPANCY_2 TC 3 in MAC 2 occupancy is not 0x0 There are packets in BRB belonging to MAC 2 traffic-class 3 BRB_REG_MAC2_TC_OCCUPANCY_3 TC 4 in MAC 2 occupancy is not 0x0 There are packets in BRB belonging to MAC 2 traffic-class 4 BRB_REG_MAC2_TC_OCCUPANCY_4 TC 0 in MAC 3 occupancy is not 0x0 There are packets in BRB belonging to MAC 3 traffic-class 0 BRB_REG_MAC3_TC_OCCUPANCY_0 TC 1 in MAC 3 occupancy is not 0x0 There are packets in BRB belonging to MAC 3 traffic-class 1 BRB_REG_MAC3_TC_OCCUPANCY_1 TC 2 in MAC 3 occupancy is not 0x0 There are packets in BRB belonging to MAC 3 traffic-class 2 BRB_REG_MAC3_TC_OCCUPANCY_2 TC 3 in MAC 3 occupancy is not 0x0 There are packets in BRB belonging to MAC 3 traffic-class 3 BRB_REG_MAC3_TC_OCCUPANCY_3 TC 4 in MAC 3 occupancy is not 0x0 There are packets in BRB belonging to MAC 3 traffic-class 4 BRB_REG_MAC3_TC_OCCUPANCY_4 NIG: Error in FIFOs accesses for port 2. NIG: Fatal NIG error NIG_REG_INT_STS_6 NIG: Pause too long interrupt occurred in port 2. NIG: PAUSE / PFC was asserted for more than a pre-defined time on port #2 NIG_REG_INT_STS_7 NIG_REG_FLOWCTRL_MODE NIG_REG_RX_FLOWCTRL_STATUS NIG: Error in FIFOs accesses for port 3. NIG: Fatal NIG error NIG_REG_INT_STS_8 NIG: Pause too long interrupt occurred in port 3. NIG: PAUSE / PFC was asserted for more than a pre-defined time on port #3 NIG_REG_INT_STS_9 NIG_REG_FLOWCTRL_MODE NIG_REG_RX_FLOWCTRL_STATUS NIG: Data path parity error occurred. NIG: Data path parity error occurred. NIG_REG_PRTY_STS NIG_REG_RX_PARITY_ERR NIG_REG_TX_PARITY_ERR NIG_REG_LB_PARITY_ERR NWS: CM1_OK_0 is 0 : No 10Gb clock NWS_REG_COMMON_STATUS NWS: CM0_OK_0 is 0 : No 25Gb clock NWS_REG_COMMON_STATUS NWS: Ethernet Phy asserting ERR_O NWS_REG_COMMON_STATUS NWS: Interrupt status is not 0 : Address Error NWS_REG_INT_STS_0 NWS: Parity status 0 is not 0 NWS_REG_PRTY_STS_H_0 NWM: Interrupt status is not 0 : Address Error NWM_REG_INT_STS NWM: Interrupt status is not 0 : TX Fifo underflow or overflow set NWM_REG_INT_STS NWM: Parity status 0 is not 0 NWM_REG_PRTY_STS_H_0 NWM: Parity status 1 is not 0 NWM_REG_PRTY_STS_H_1 NWM: Parity status 2 is not 0 NWM_REG_PRTY_STS_H_2 BTB: Interrupt status 0 is set BTB: Fatal BTB error BTB_REG_INT_STS_0 BTB_REG_STOPPED_RD_REQ BTB_REG_STOPPED_RLS_REQ BTB: Interrupt status 4 is set BTB: Fatal BTB error BTB_REG_INT_STS_4 BTB_REG_STOPPED_RD_REQ BTB_REG_STOPPED_RLS_REQ BTB: Read packet client 4 FIFOs are not empty BTB: Read packet main port #2 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_4 BTB: Read packet client 5 FIFOs are not empty BTB: Read packet LB port #2 client 1 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_5 BTB: Read packet client 6 FIFOs are not empty BTB: Read packet main port #3 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_6 BTB: Read packet client 7 FIFOs are not empty BTB: Read packet LB port #3 client 1 FIFOs are not empty BTB_REG_RC_PKT_EMPTY_7 XCM: QM Active State Counter is not 0 XCM_REG_QM_ACT_ST_CNT XSEM: VF error vector is not zero XSEM: Error was returned for one or more VF/s XSEM_REG_VF_ERR_VECTOR YSEM: VF error vector is not zero YSEM: Error was returned for one or more VF/s YSEM_REG_VF_ERR_VECTOR PSEM: VF error vector is not zero PSEM: Error was returned for one or more VF/s PSEM_REG_VF_ERR_VECTOR TSEM: VF error vector is not zero TSEM: Error was returned for one or more VF/s TSEM_REG_VF_ERR_VECTOR MSEM: VF error vector is not zero MSEM: Error was returned for one or more VF/s MSEM_REG_VF_ERR_VECTOR USEM: VF error vector is not zero USEM: Error was returned for one or more VF/s USEM_REG_VF_ERR_VECTOR PCIE: ucorr_err_status is not 0 PGLCS_REG_PGL_CS_UC_ERR_STATUS PCIE: ucorr_err_status - Unsupported request error PGLCS_REG_PGL_CS_UC_ERR_STATUS PCIE: ucorr_err_status - Flow Control Protocol Error PGLCS_REG_PGL_CS_UC_ERR_STATUS PCIE: error packet header is not 0 PGLCS_REG_PGL_CS_HEADER_LOG1 PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0. PGLCS_REG_PGL_CS_TL_CTRLSTAT_5 PCIE: Func 0 1: attentions register is not 0x2040902 PGLCS_REG_PGL_CS_TL_CTRLSTAT_5 PCIE: Func 2 3 4: attentions register is not 0x10240902 PGLCS_REG_PGL_CS_TL_FUNC345_STAT PCIE: Func 5 6 7: attentions register is not 0x10240902 PGLCS_REG_PGL_CS_TL_FUNC678_STAT PCIE: Overflow in DLP2TLP buffer PGLCS_REG_PGL_CS_DLATTN_VEC MISCS: interrupt status 1 is not 0. MISCS_REG_INT_STS_1 IGU: Parity status 1 is not 0 IGU_REG_PRTY_STS_H_1 NIG: RX MAC FIFO for the port is not empty NIG: RX FIFO for receiving data from MAC is not empty NIG_REG_RX_MACFIFO_EMPTY XYLD: Parity status is not 0 XYLD_REG_PRTY_STS_H_0 YULD : Pending Message counter to External event1 is not 0 YULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR YULD : Pending Message counter to External event2 is not 0 YULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR YULD : Pending Message counter to External event3 is not 0 YULD: There are outstanding messages waiting for 'done' indication from MCM YULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR YULD : Pending Message counter to External event4 is not 0 YULD: There are outstanding messages waiting for 'done' indication from YCM YULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR YULD : Pending Message counter to External event5 is not 0 YULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR YULD: YULD_REG_FOC_REMAIN_CREDITS is not YULD_REG_FOCI_FOC_CREDITS YULD: UCM didn't ACK all the message cycles sent by YULD YULD_REG_FOC_REMAIN_CREDITS YULD_REG_FOCI_FOC_CREDITS YULD : CCFC REQ Pending Message counter is not 0 YULD:There are outstanding CCFC load requests YULD_REG_DBG_PENDING_CCFC_REQ YULD : TCFC REQ Pending Message counter is not 0 YULD:There are outstanding TCFC load requests YULD_REG_DBG_PENDING_TCFC_REQ YULD: Parity status is not 0 YULD_REG_PRTY_STS_H_0 TMLD: Parity status is not 0 TMLD_REG_PRTY_STS_H_0 MULD: Parity status is not 0 MULD_REG_PRTY_STS_H_0 MCP2: ROM Parity status is not 0 MCP2_REG_PRTY_STS MCP2: Parity status is not 0 MCP2_REG_PRTY_STS_H_0 NCSI: Parity status is not 0 NCSI_REG_PRTY_STS_H_0 UMAC: Interrupt status is not 0 : TX_OVERFLOW UMAC_REG_INT_STS UMAC: Interrupt status is not 0 : Address Error UMAC_REG_INT_STS NWS: ERR_CTRL0 is not 0 : An error ocurred NWS_REG_NWS_CMU_PHY0_TOP_ERR_CTRL0 NWS: ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_PHY0_TOP_ERR_CTRL1 NWS: ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_PHY0_TOP_ERR_CTRL2 NWS: REGBUS_ERR_INFO_STATUS0 is not 0 : err_type[0:1](1=err_ack;2=timeout) : transfer_rw[2](1=write;0=read) NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS0 NWS: REGBUS_ERR_INFO_STATUS0 is not 0 : register err_ack NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS0 NWS: REGBUS_ERR_INFO_STATUS0 is not 0 : register timeout NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS0 NWS: REGBUS_ERR_INFO_STATUS0 is not 0 : error was on register write NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS0 NWS: REGBUS_ERR_INFO_STATUS1 is not 0 : errored register transfer address lsb NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS1 NWS: REGBUS_ERR_INFO_STATUS2 is not 0 : errored register transfer address msb NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS2 NWS: REGBUS_ERR_INFO_STATUS3 is not 0 : errored register transfer write data NWS_REG_NWS_CMU_PHY0_TOP_REGBUS_ERR_INFO_STATUS3 NWS: CMU0 cmu_ok is not 1 NWS_REG_NWS_CMU_CMU_LC0_TOP_PHY_IF_STATUS NWS: CMU0 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_CMU_LC0_TOP_ERR_CTRL1 NWS: CMU0 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_CMU_LC0_TOP_ERR_CTRL2 NWS: CMU0 ERR_CTRL2 is not 0 : A critical error occurred preventing cm0_ok_o from asserting NWS_REG_NWS_CMU_CMU_LC0_TOP_ERR_CTRL3 NWS: CMU1 cmu_ok is not 1 NWS_REG_NWS_CMU_CMU_R0_TOP_PHY_IF_STATUS NWS: CMU1 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_CMU_R0_TOP_ERR_CTRL1 NWS: CMU1 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_CMU_R0_TOP_ERR_CTRL2 NWS: CMU1 ERR_CTRL2 is not 0 : A critical error occurred preventing cm1_ok_o from asserting NWS_REG_NWS_CMU_CMU_R0_TOP_ERR_CTRL3 NWS: ln0_ok is not 1 NWS_REG_NWS_CMU_LN0_TOP_PHY_IF_STATUS NWS: ln0 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_LN0_TOP_ERR_CTRL1 NWS: ln0 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_LN0_TOP_ERR_CTRL2 NWS: ln0_error is not 0 : lane_err NWS_REG_NWS_CMU_LN0_TOP_ERR_CTRL3 NWS: ln1_ok is not 1 NWS_REG_NWS_CMU_LN1_TOP_PHY_IF_STATUS NWS: ln1 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_LN1_TOP_ERR_CTRL1 NWS: ln1 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_LN1_TOP_ERR_CTRL2 NWS: ln1_error is not 0 : lane_err NWS_REG_NWS_CMU_LN1_TOP_ERR_CTRL3 NWS: ln2_ok is not 1 NWS_REG_NWS_CMU_LN2_TOP_PHY_IF_STATUS NWS: ln2 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_LN2_TOP_ERR_CTRL1 NWS: ln2 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_LN2_TOP_ERR_CTRL2 NWS: ln2_error is not 0 : lane_err NWS_REG_NWS_CMU_LN2_TOP_ERR_CTRL3 NWS: ln3_ok is not 1 NWS_REG_NWS_CMU_LN3_TOP_PHY_IF_STATUS NWS: ln3 ERR_CTRL1 is not 0 : err_code_7_0 NWS_REG_NWS_CMU_LN3_TOP_ERR_CTRL1 NWS: ln3 ERR_CTRL2 is not 0 : err_code_15_8 NWS_REG_NWS_CMU_LN3_TOP_ERR_CTRL2 NWS: ln3_error is not 0 : lane_err NWS_REG_NWS_CMU_LN3_TOP_ERR_CTRL3 IPC: Parity status is not 0 IPC_REG_PRTY_STS address_error timeout_event global_reserved_address path_isolation_error trace_fifo_valid_data mem003_i_mem_prty mem002_i_mem_prty generic_sw cnig_interrupt opte_dorq_fifo_err_eng1 opte_dorq_fifo_err_eng0 opte_dbg_fifo_err_eng1 opte_dbg_fifo_err_eng0 opte_btb_if1_fifo_err_eng1 opte_btb_if1_fifo_err_eng0 opte_btb_if0_fifo_err_eng1 opte_btb_if0_fifo_err_eng0 opte_btb_sop_fifo_err_eng1 opte_btb_sop_fifo_err_eng0 opte_storm_fifo_err_eng0 cnig_parity incorrect_rcv_behavior was_error_attn vf_length_violation_attn vf_grc_space_violation_attn tcpl_error_attn tcpl_in_two_rcbs_attn cssnoop_fifo_overflow tcpl_translation_size_different pcie_rx_l0s_timeout master_zlr_attn admin_window_violation_attn out_of_range_function_in_pretend illegal_address pgl_cpl_err pgl_txw_of pgl_cpl_aft pgl_cpl_of pgl_cpl_ecrc pgl_pcie_attn pgl_read_blocked pgl_write_blocked vf_ilt_err rxobffexception_attn datapath_registers mem027_i_mem_prty mem007_i_mem_prty mem009_i_mem_prty mem010_i_mem_prty mem008_i_mem_prty mem022_i_mem_prty mem023_i_mem_prty mem024_i_mem_prty mem025_i_mem_prty mem004_i_mem_prty mem005_i_mem_prty mem011_i_mem_prty mem016_i_mem_prty mem017_i_mem_prty mem012_i_mem_prty mem013_i_mem_prty mem014_i_mem_prty mem015_i_mem_prty mem018_i_mem_prty mem020_i_mem_prty mem021_i_mem_prty mem019_i_mem_prty mem026_i_mem_prty mem006_i_mem_prty mem002_i_mem_prty_0 mem002_i_mem_prty_1 mem002_i_mem_prty_2 mem002_i_mem_prty_3 mem002_i_mem_prty_4 mem002_i_mem_prty_5 mem002_i_mem_prty_6 mem002_i_mem_prty_7 mem001_i_mem_prty tx_illegal_sop_port0 tx_illegal_sop_port1 tx_illegal_sop_port2 tx_illegal_sop_port3 tdm_lane_0_bandwith_exceed tdm_lane_1_bandwith_exceed pmeg_intr pmfc_intr fifo_error datapath_tx datapath_rx datapath_parity_error rc_pkt0_rls_error rc_pkt0_protocol_error rc_pkt1_rls_error rc_pkt1_protocol_error rc_pkt2_rls_error rc_pkt2_protocol_error rc_pkt3_rls_error rc_pkt3_protocol_error rc_sop_req_tc_port_error wc0_protocol_error wc1_protocol_error wc2_protocol_error wc3_protocol_error ll_blk_error mac0_fc_cnt_error ll_arb_calc_error wc0_inp_fifo_error wc0_sop_fifo_error wc0_len_fifo_error wc0_queue_fifo_error wc0_free_point_fifo_error wc0_next_point_fifo_error wc0_strt_fifo_error wc0_second_dscr_fifo_error wc0_pkt_avail_fifo_error wc0_cos_cnt_fifo_error wc0_notify_fifo_error wc0_ll_req_fifo_error wc0_ll_pa_cnt_error wc0_bb_pa_cnt_error wc1_inp_fifo_error wc1_sop_fifo_error wc1_queue_fifo_error wc1_free_point_fifo_error wc1_next_point_fifo_error wc1_strt_fifo_error wc1_second_dscr_fifo_error wc1_pkt_avail_fifo_error wc1_cos_cnt_fifo_error wc1_notify_fifo_error wc1_ll_req_fifo_error wc1_ll_pa_cnt_error wc1_bb_pa_cnt_error wc2_inp_fifo_error wc2_sop_fifo_error wc2_queue_fifo_error wc2_free_point_fifo_error wc2_next_point_fifo_error wc2_strt_fifo_error wc2_second_dscr_fifo_error wc2_pkt_avail_fifo_error wc2_cos_cnt_fifo_error wc2_notify_fifo_error wc2_ll_req_fifo_error wc2_ll_pa_cnt_error wc2_bb_pa_cnt_error wc3_inp_fifo_error wc3_sop_fifo_error wc3_queue_fifo_error wc3_free_point_fifo_error wc3_next_point_fifo_error wc3_strt_fifo_error wc3_second_dscr_fifo_error wc3_pkt_avail_fifo_error wc3_cos_cnt_fifo_error wc3_notify_fifo_error wc3_ll_req_fifo_error wc3_ll_pa_cnt_error wc3_bb_pa_cnt_error rc_pkt0_side_fifo_error rc_pkt0_req_fifo_error rc_pkt0_blk_fifo_error rc_pkt0_rls_left_fifo_error rc_pkt0_strt_ptr_fifo_error rc_pkt0_second_ptr_fifo_error rc_pkt0_rsp_fifo_error rc_pkt0_dscr_fifo_error rc_pkt1_side_fifo_error rc_pkt1_req_fifo_error rc_pkt1_blk_fifo_error rc_pkt1_rls_left_fifo_error rc_pkt1_strt_ptr_fifo_error rc_pkt1_second_ptr_fifo_error rc_pkt1_rsp_fifo_error rc_pkt1_dscr_fifo_error rc_pkt2_side_fifo_error rc_pkt2_req_fifo_error rc_pkt2_blk_fifo_error rc_pkt2_rls_left_fifo_error rc_pkt2_strt_ptr_fifo_error rc_pkt2_second_ptr_fifo_error rc_pkt2_rsp_fifo_error rc_pkt2_dscr_fifo_error rc_pkt3_side_fifo_error rc_pkt3_req_fifo_error rc_pkt3_blk_fifo_error rc_pkt3_rls_left_fifo_error rc_pkt3_strt_ptr_fifo_error rc_pkt3_second_ptr_fifo_error rc_pkt3_rsp_fifo_error rc_pkt3_dscr_fifo_error rc_sop_strt_fifo_error rc_sop_req_fifo_error rc_sop_dscr_fifo_error rc_sop_queue_fifo_error ll_arb_rls_fifo_error ll_arb_prefetch_fifo_error rc_pkt0_rls_fifo_error rc_pkt1_rls_fifo_error rc_pkt2_rls_fifo_error rc_pkt3_rls_fifo_error rc_pkt4_rls_fifo_error rc_pkt5_rls_fifo_error rc_pkt6_rls_fifo_error rc_pkt7_rls_fifo_error rc_pkt8_rls_fifo_error rc_pkt9_rls_fifo_error rc_pkt4_rls_error rc_pkt4_protocol_error rc_pkt4_side_fifo_error rc_pkt4_req_fifo_error rc_pkt4_blk_fifo_error rc_pkt4_rls_left_fifo_error rc_pkt4_strt_ptr_fifo_error rc_pkt4_second_ptr_fifo_error rc_pkt4_rsp_fifo_error rc_pkt4_dscr_fifo_error rc_pkt5_rls_error rc_pkt5_protocol_error rc_pkt5_side_fifo_error rc_pkt5_req_fifo_error rc_pkt5_blk_fifo_error rc_pkt5_rls_left_fifo_error rc_pkt5_strt_ptr_fifo_error rc_pkt5_second_ptr_fifo_error rc_pkt5_rsp_fifo_error rc_pkt5_dscr_fifo_error rc_pkt6_rls_error rc_pkt6_protocol_error rc_pkt6_side_fifo_error rc_pkt6_req_fifo_error rc_pkt6_blk_fifo_error rc_pkt6_rls_left_fifo_error rc_pkt6_strt_ptr_fifo_error rc_pkt6_second_ptr_fifo_error rc_pkt6_rsp_fifo_error rc_pkt6_dscr_fifo_error rc_pkt7_rls_error rc_pkt7_protocol_error rc_pkt7_side_fifo_error rc_pkt7_req_fifo_error rc_pkt7_blk_fifo_error rc_pkt7_rls_left_fifo_error rc_pkt7_strt_ptr_fifo_error rc_pkt7_second_ptr_fifo_error rc_pkt7_rsp_fifo_error packet_available_sync_fifo_push_error rc_pkt8_rls_error rc_pkt8_protocol_error rc_pkt8_side_fifo_error rc_pkt8_req_fifo_error rc_pkt8_blk_fifo_error rc_pkt8_rls_left_fifo_error rc_pkt8_strt_ptr_fifo_error rc_pkt8_second_ptr_fifo_error rc_pkt8_rsp_fifo_error rc_pkt8_dscr_fifo_error rc_pkt9_rls_error rc_pkt9_protocol_error rc_pkt9_side_fifo_error rc_pkt9_req_fifo_error rc_pkt9_blk_fifo_error rc_pkt9_rls_left_fifo_error rc_pkt9_strt_ptr_fifo_error rc_pkt9_second_ptr_fifo_error rc_pkt9_rsp_fifo_error rc_pkt9_dscr_fifo_error wc4_protocol_error wc5_protocol_error wc6_protocol_error wc7_protocol_error wc8_protocol_error wc9_protocol_error wc4_inp_fifo_error wc4_sop_fifo_error wc4_queue_fifo_error wc4_free_point_fifo_error wc4_next_point_fifo_error wc4_strt_fifo_error wc4_second_dscr_fifo_error wc4_pkt_avail_fifo_error wc4_cos_cnt_fifo_error wc4_notify_fifo_error wc4_ll_req_fifo_error wc4_ll_pa_cnt_error wc4_bb_pa_cnt_error wc5_inp_fifo_error wc5_sop_fifo_error wc5_queue_fifo_error wc5_free_point_fifo_error wc5_next_point_fifo_error wc5_strt_fifo_error wc5_second_dscr_fifo_error wc5_pkt_avail_fifo_error wc5_cos_cnt_fifo_error wc5_notify_fifo_error wc5_ll_req_fifo_error wc5_ll_pa_cnt_error wc5_bb_pa_cnt_error wc6_inp_fifo_error wc6_sop_fifo_error wc6_queue_fifo_error wc6_free_point_fifo_error wc6_next_point_fifo_error wc6_strt_fifo_error wc6_second_dscr_fifo_error wc6_pkt_avail_fifo_error wc6_cos_cnt_fifo_error wc6_notify_fifo_error wc6_ll_req_fifo_error wc6_ll_pa_cnt_error wc6_bb_pa_cnt_error wc7_inp_fifo_error wc7_sop_fifo_error wc7_queue_fifo_error wc7_free_point_fifo_error wc7_next_point_fifo_error wc7_strt_fifo_error wc7_second_dscr_fifo_error wc7_pkt_avail_fifo_error wc7_cos_cnt_fifo_error wc7_notify_fifo_error wc7_ll_req_fifo_error wc7_ll_pa_cnt_error wc7_bb_pa_cnt_error wc8_inp_fifo_error wc8_sop_fifo_error wc8_queue_fifo_error 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is_grc_under_err0 is_grc_ovfl_err1 is_grc_under_err1 is_grc_ovfl_err2 is_grc_under_err2 is_grc_ovfl_err3 is_grc_under_err3 in_prcs_tbl_ovfl agg_con_data_buf_ovfl agg_con_cmd_buf_ovfl sm_con_data_buf_ovfl sm_con_cmd_buf_ovfl agg_task_data_buf_ovfl agg_task_cmd_buf_ovfl sm_task_data_buf_ovfl sm_task_cmd_buf_ovfl fi_desc_input_violate se_desc_input_violate qmreg_more4 mem026_i_ecc_rf_int mem003_i_ecc_0_rf_int mem003_i_ecc_1_rf_int mem022_i_ecc_0_rf_int mem022_i_ecc_1_rf_int mem005_i_ecc_0_rf_int mem005_i_ecc_1_rf_int mem024_i_ecc_0_rf_int mem024_i_ecc_1_rf_int mem021_i_ecc_0_rf_int mem021_i_ecc_1_rf_int mem023_i_ecc_0_rf_int mem023_i_ecc_1_rf_int is_msdm_ovfl_err is_msdm_under_err is_ysdm_ovfl_err is_ysdm_under_err is_usdm_ovfl_err is_usdm_under_err is_tmld_ovfl_err is_tmld_under_err is_usem_ovfl_err is_usem_under_err mem028_i_ecc_rf_int mem025_i_ecc_0_rf_int mem025_i_ecc_1_rf_int is_xsdm_ovfl_err is_xsdm_under_err is_rdif_ovfl_err is_rdif_under_err is_tdif_ovfl_err is_tdif_under_err is_muld_ovfl_err is_muld_under_err is_yuld_ovfl_err is_yuld_under_err mem030_i_ecc_rf_int mem007_i_ecc_0_rf_int mem007_i_ecc_1_rf_int mem027_i_ecc_0_rf_int mem027_i_ecc_1_rf_int qm_act_st_cnt_msg_prcs_under qm_act_st_cnt_msg_prcs_ovfl qm_act_st_cnt_ext_ld_under qm_act_st_cnt_ext_ld_ovfl qm_act_st_cnt_rbc_under qm_act_st_cnt_rbc_ovfl qm_act_st_cnt_drop_under qm_act_st_cnt_illeg_pqnum mem036_i_ecc_rf_int mem003_i_ecc_2_rf_int mem003_i_ecc_3_rf_int mem033_i_ecc_0_rf_int mem033_i_ecc_1_rf_int mem034_i_ecc_rf_int mem035_i_ecc_rf_int mem032_i_ecc_0_rf_int mem032_i_ecc_1_rf_int mem033_i_ecc_rf_int is_xyld_ovfl_err is_xyld_under_err mem027_i_ecc_rf_int is_psdm_ovfl_err is_psdm_under_err mem010_i_ecc_0_rf_int mem010_i_ecc_1_rf_int mem009_i_ecc_0_rf_int mem009_i_ecc_1_rf_int ovf_err_tx ovf_err_other pf_usg_cnt_err vf_usg_cnt_err voq_crd_inc_err voq_crd_dec_err byte_crd_inc_err byte_crd_dec_err err_incdec_rlglblcrd err_incdec_rlpfcrd err_incdec_wfqpfcrd err_incdec_wfqvpcrd err_incdec_voqlinecrd err_incdec_voqbytecrd fifos_error qm_rl_dc_exp_pf_controler_pop_error qm_rl_dc_exp_pf_controler_push_error qm_rl_dc_rf_req_controler_pop_error qm_rl_dc_rf_req_controler_push_error qm_rl_dc_rf_res_controler_pop_error qm_rl_dc_rf_res_controler_push_error xcm_wrc_fifo ucm_wrc_fifo tcm_wrc_fifo ccm_wrc_fifo bigramhigh bigramlow base_address wrbuff bigramhigh_ext_a bigramlow_ext_a base_address_ext_a mem062_i_mem_prty mem061_i_mem_prty mem063_i_mem_prty mem064_i_mem_prty mem007_i_mem_prty_9 mem007_i_mem_prty_10 mem007_i_mem_prty_11 mem007_i_mem_prty_12 mem007_i_mem_prty_13 mem007_i_mem_prty_14 mem007_i_mem_prty_15 pxp_read_data_fifo_ov pxp_read_data_fifo_un pxp_read_ctrl_fifo_ov pxp_read_ctrl_fifo_un cfc_load_command_fifo_ov cfc_load_command_fifo_un cfc_load_echo_fifo_ov cfc_load_echo_fifo_un client_out_fifo_ov client_out_fifo_un ac_command_fifo_ov ac_command_fifo_un client_in_pbf_fifo_ov client_in_pbf_fifo_un client_in_ucm_fifo_ov client_in_ucm_fifo_un client_in_tcm_fifo_ov client_in_tcm_fifo_un client_in_xcm_fifo_ov client_in_xcm_fifo_un expiration_cmd_fifo_ov expiration_cmd_fifo_un stop_all_lc_invalid command_lc_invalid_0 command_lc_invalid_1 init_command_lc_valid stop_all_exp_lc_valid command_cid_invalid_0 reserved_command command_cid_invalid_1 cload_res_loaderr_conn cload_res_loadcancel_conn cload_res_validerr_conn context_rd_last context_wr_last pxp_rd_data_eop_bvalid pend_conn_scan pend_task_scan pxp_rd_data_eop_error cload_res_loaderr_task cload_res_loadcancel_task cload_res_validerr_task mem012_i_ecc_0_rf_int mem012_i_ecc_1_rf_int db_drop dorq_fifo_ovfl_err dorq_fifo_afull cfc_byp_validation_err cfc_ld_resp_err xcm_done_cnt_err cfc_ld_req_fifo_ovfl_err cfc_ld_req_fifo_under_err rc_pkt0_1st_error rc_pkt0_len_error rc_pkt0_middle_error rc_pkt1_1st_error rc_pkt1_len_error rc_pkt1_middle_error rc_pkt2_1st_error rc_pkt2_len_error rc_pkt2_middle_error rc_pkt3_1st_error rc_pkt3_len_error rc_pkt3_middle_error uncomplient_lossless_error ll_arb_prefetch_sop_error packet_counter_error byte_counter_error mac1_fc_cnt_error wc0_eop_fifo_error wc1_eop_fifo_error wc2_eop_fifo_error wc3_eop_fifo_error rc0_eop_error rc1_eop_error rc_pkt4_1st_error rc_pkt4_len_error rc_pkt4_middle_error rc_sop_inp_sync_fifo_push_error rc0_inp_sync_fifo_push_error rc1_inp_sync_fifo_push_error rc2_inp_sync_fifo_push_error rc3_inp_sync_fifo_push_error rc0_out_sync_fifo_push_error rc1_out_sync_fifo_push_error rc2_out_sync_fifo_push_error rc3_out_sync_fifo_push_error rc4_out_sync_fifo_push_error rc0_eop_inp_sync_fifo_push_error rc1_eop_inp_sync_fifo_push_error rc2_eop_inp_sync_fifo_push_error rc3_eop_inp_sync_fifo_push_error rc0_eop_out_sync_fifo_push_error rc1_eop_out_sync_fifo_push_error rc2_eop_out_sync_fifo_push_error rc3_eop_out_sync_fifo_push_error rc2_eop_error rc3_eop_error mac2_fc_cnt_error mac3_fc_cnt_error wc4_eop_fifo_error wc5_eop_fifo_error wc6_eop_fifo_error wc7_eop_fifo_error mem070_i_mem_prty mem069_i_mem_prty mem065_i_mem_prty mem066_i_mem_prty mem067_i_mem_prty mem068_i_mem_prty lcid_validation_err cam_parity gft_cam_parity inp_queue_error delay_fifo_error async_host_error prm_fifo_error ccfc_load_pend_error tcfc_load_pend_error dst_int_ram_wait_error dst_pas_buf_wait_error dst_pxp_immed_error dst_pxp_dst_pend_error dst_brb_src_pend_error dst_brb_src_addr_error rsp_brb_pend_error rsp_int_ram_pend_error rsp_brb_rd_data_error rsp_int_ram_rd_data_error rsp_pxp_rd_data_error cm_delay_error sh_delay_error cmpl_pend_error cprm_pend_error timer_addr_error timer_pend_error dorq_dpm_error dst_pxp_done_error xcm_rmt_buffer_error ycm_rmt_buffer_error fic_last_error fic_length_error fic_fifo_error pas_buf_fifo_error sync_fin_pop_error sync_dra_wr_push_error sync_dra_wr_pop_error sync_dra_rd_push_error sync_dra_rd_pop_error sync_fin_push_error sem_fast_address_error cam_lsb_inp_fifo cam_msb_inp_fifo cam_out_fifo fin_fifo thread_fifo_error thread_overrun sync_ext_store_push_error sync_ext_store_pop_error sync_ext_load_push_error sync_ext_load_pop_error sync_ram_rd_push_error sync_ram_rd_pop_error sync_ram_wr_pop_error sync_ram_wr_push_error sync_dbg_push_error sync_dbg_pop_error dbg_fifo_error cam_msb2_inp_fifo vfc_interrupt vfc_out_fifo_error storm_stack_uf_attn storm_stack_of_attn storm_runtime_error ext_load_pend_wr_error thread_rls_orun_error thread_rls_aloc_error thread_rls_vld_error ext_thread_oor_error ord_id_fifo_error invld_foc_error ext_ld_len_error thrd_ord_fifo_error invld_thrd_ord_error vfc_rbc_parity_error storm_rf_parity_error reg_gen_parity_error msg_inp_cnt_error msg_out_cnt_error inp_state_error out_state_error main_state_error calc_state_error inp_fifo_error cmd_fifo_error msg_fifo_error rsp_fifo_error hdr_fifo_error ld_hdr_err ld_seg_msg_err ld_tid_mini_cache_err ld_cid_mini_cache_err ld_long_message ififo_error immed_fifo_error ofst_pend_error pad_pend_error pbinp_pend_error tag_pend_error mstorm_eop_err ustorm_eop_err mstorm_que_err ustorm_que_err eop_error pfifo_error db_buf_error th_exec_error tq_error_wr tq_error_rd_th tq_error_rd_ih fc_alm_calc_error wc_dup_upd_data_fifo_error wc_dup_rsp_dscr_fifo_error wc_dup_upd_point_fifo_error wc_dup_pkt_avail_fifo_error wc_dup_pkt_avail_cnt_error rc_pkt5_len_error rc_pkt6_len_error rc_pkt7_len_error wc0_sync_fifo_push_error rls_sync_fifo_push_error mem041_i_ecc_rf_int mem042_i_ecc_rf_int mem012_i_ecc_2_rf_int mem012_i_ecc_3_rf_int mem012_i_ecc_4_rf_int mem012_i_ecc_5_rf_int mem012_i_ecc_6_rf_int mem012_i_ecc_7_rf_int mem012_i_ecc_8_rf_int mem012_i_ecc_9_rf_int mem012_i_ecc_10_rf_int mem012_i_ecc_11_rf_int mem012_i_ecc_12_rf_int mem012_i_ecc_13_rf_int mem012_i_ecc_14_rf_int mem012_i_ecc_15_rf_int fatal_dix_err fatal_config_err cmd_fifo_err order_fifo_err rdata_fifo_err dif_stop_err partial_dif_w_eob l1_dirty_bit ccfc_ld_l1_num_error tcfc_ld_l1_num_error ccfc_wb_l1_num_error tcfc_wb_l1_num_error ccfc_cvld_error tcfc_cvld_error bvalid_error exe_error ccam_par_err scam_par_err lc_que_ram_porta_lsb_par_err lc_que_ram_porta_msb_par_err lc_que_ram_portb_lsb_par_err lc_que_ram_portb_msb_par_err ctrl_fifo_error_err pxp_req_length_too_big host_tries2access_prod_upd vf_tries2acc_attn_cmd mme_bigger_then_5 sb_index_is_not_valid durin_int_read_with_simd_dis cmd_fid_not_match segment_access_invalid attn_prod_acc mem008_i_mem_prty_0 mem008_i_mem_prty_1 mem008_i_mem_prty_2 mem012_i_mem_prty_0 unauthorized_pxp_rd_cmd unauthorized_pxp_length_cmd pxp_sb_address_error pxp_pi_number_error cleanup_reg_sb_idx_error fsm_invalid_line cqe_fifo_err igu_wdata_fifo_err igu_req_fifo_err igu_cmd_fifo_err mem001_i_ecc_0_rf_int mem001_i_ecc_1_rf_int tx_overflow debug_fifo_error dorq_fifo_error dbg_syncfifo_error_wr dorq_syncfifo_error_wr storm_syncfifo_error_wr dbgmux_syncfifo_error_wr msdm_syncfifo_error_wr tsdm_syncfifo_error_wr usdm_syncfifo_error_wr xsdm_syncfifo_error_wr ysdm_syncfifo_error_wr tx_sopq0_error tx_sopq1_error tx_sopq2_error tx_sopq3_error tx_sopq4_error tx_sopq5_error tx_sopq6_error tx_sopq7_error tx_sopq8_error tx_sopq9_error tx_sopq10_error tx_sopq11_error tx_sopq12_error tx_sopq13_error tx_sopq14_error tx_sopq15_error lb_sopq0_error lb_sopq1_error lb_sopq2_error lb_sopq3_error lb_sopq4_error lb_sopq5_error lb_sopq6_error lb_sopq7_error lb_sopq8_error lb_sopq9_error lb_sopq10_error lb_sopq11_error lb_sopq12_error lb_sopq13_error lb_sopq14_error lb_sopq15_error p0_purelb_sopq_error p0_rx_macfifo_error p0_tx_macfifo_error p0_tx_bmb_fifo_error p0_lb_bmb_fifo_error p0_tx_btb_fifo_error p0_lb_btb_fifo_error p0_rx_llh_dfifo_error p0_tx_llh_dfifo_error p0_lb_llh_dfifo_error p0_rx_llh_hfifo_error p0_tx_llh_hfifo_error p0_lb_llh_hfifo_error p0_rx_llh_rfifo_error p0_tx_llh_rfifo_error p0_lb_llh_rfifo_error p0_storm_fifo_error p0_storm_dscr_fifo_error p0_tx_gnt_fifo_error p0_lb_gnt_fifo_error p0_tx_pause_too_long_int p0_tc0_pause_too_long_int p0_tc1_pause_too_long_int p0_tc2_pause_too_long_int p0_tc3_pause_too_long_int p0_tc4_pause_too_long_int p0_tc5_pause_too_long_int p0_tc6_pause_too_long_int p0_tc7_pause_too_long_int p0_lb_tc0_pause_too_long_int p0_lb_tc1_pause_too_long_int p0_lb_tc2_pause_too_long_int p0_lb_tc3_pause_too_long_int p0_lb_tc4_pause_too_long_int p0_lb_tc5_pause_too_long_int p0_lb_tc6_pause_too_long_int p0_lb_tc7_pause_too_long_int p0_lb_tc8_pause_too_long_int p1_purelb_sopq_error p1_rx_macfifo_error p1_tx_macfifo_error p1_tx_bmb_fifo_error p1_lb_bmb_fifo_error p1_tx_btb_fifo_error p1_lb_btb_fifo_error p1_rx_llh_dfifo_error p1_tx_llh_dfifo_error p1_lb_llh_dfifo_error p1_rx_llh_hfifo_error p1_tx_llh_hfifo_error p1_lb_llh_hfifo_error p1_rx_llh_rfifo_error p1_tx_llh_rfifo_error p1_lb_llh_rfifo_error p1_storm_fifo_error p1_storm_dscr_fifo_error p1_tx_gnt_fifo_error p1_lb_gnt_fifo_error p1_tx_pause_too_long_int p1_tc0_pause_too_long_int p1_tc1_pause_too_long_int p1_tc2_pause_too_long_int p1_tc3_pause_too_long_int p1_tc4_pause_too_long_int p1_tc5_pause_too_long_int p1_tc6_pause_too_long_int p1_tc7_pause_too_long_int p1_lb_tc0_pause_too_long_int p1_lb_tc1_pause_too_long_int p1_lb_tc2_pause_too_long_int p1_lb_tc3_pause_too_long_int p1_lb_tc4_pause_too_long_int p1_lb_tc5_pause_too_long_int p1_lb_tc6_pause_too_long_int p1_lb_tc7_pause_too_long_int p1_lb_tc8_pause_too_long_int p2_purelb_sopq_error p2_rx_macfifo_error p2_tx_macfifo_error p2_tx_bmb_fifo_error p2_lb_bmb_fifo_error p2_tx_btb_fifo_error p2_lb_btb_fifo_error p2_rx_llh_dfifo_error p2_tx_llh_dfifo_error p2_lb_llh_dfifo_error p2_rx_llh_hfifo_error p2_tx_llh_hfifo_error p2_lb_llh_hfifo_error p2_rx_llh_rfifo_error p2_tx_llh_rfifo_error p2_lb_llh_rfifo_error p2_storm_fifo_error p2_storm_dscr_fifo_error p2_tx_gnt_fifo_error p2_lb_gnt_fifo_error p2_tx_pause_too_long_int p2_tc0_pause_too_long_int p2_tc1_pause_too_long_int p2_tc2_pause_too_long_int p2_tc3_pause_too_long_int p2_tc4_pause_too_long_int p2_tc5_pause_too_long_int p2_tc6_pause_too_long_int p2_tc7_pause_too_long_int p2_lb_tc0_pause_too_long_int p2_lb_tc1_pause_too_long_int p2_lb_tc2_pause_too_long_int p2_lb_tc3_pause_too_long_int p2_lb_tc4_pause_too_long_int p2_lb_tc5_pause_too_long_int p2_lb_tc6_pause_too_long_int p2_lb_tc7_pause_too_long_int p2_lb_tc8_pause_too_long_int p3_purelb_sopq_error p3_rx_macfifo_error p3_tx_macfifo_error p3_tx_bmb_fifo_error p3_lb_bmb_fifo_error p3_tx_btb_fifo_error p3_lb_btb_fifo_error p3_rx_llh_dfifo_error p3_tx_llh_dfifo_error p3_lb_llh_dfifo_error p3_rx_llh_hfifo_error p3_tx_llh_hfifo_error p3_lb_llh_hfifo_error p3_rx_llh_rfifo_error p3_tx_llh_rfifo_error p3_lb_llh_rfifo_error p3_storm_fifo_error p3_storm_dscr_fifo_error p3_tx_gnt_fifo_error p3_lb_gnt_fifo_error p3_tx_pause_too_long_int p3_tc0_pause_too_long_int p3_tc1_pause_too_long_int p3_tc2_pause_too_long_int p3_tc3_pause_too_long_int p3_tc4_pause_too_long_int p3_tc5_pause_too_long_int p3_tc6_pause_too_long_int p3_tc7_pause_too_long_int p3_lb_tc0_pause_too_long_int p3_lb_tc1_pause_too_long_int p3_lb_tc2_pause_too_long_int p3_lb_tc3_pause_too_long_int p3_lb_tc4_pause_too_long_int p3_lb_tc5_pause_too_long_int p3_lb_tc6_pause_too_long_int p3_lb_tc7_pause_too_long_int p3_lb_tc8_pause_too_long_int mem107_i_mem_prty mem103_i_mem_prty mem104_i_mem_prty mem105_i_mem_prty mem106_i_mem_prty mem072_i_mem_prty mem071_i_mem_prty mem074_i_mem_prty mem073_i_mem_prty mem076_i_mem_prty mem075_i_mem_prty mem078_i_mem_prty mem077_i_mem_prty mem090_i_mem_prty mem089_i_mem_prty mem092_i_mem_prty mem091_i_mem_prty mem109_i_mem_prty mem110_i_mem_prty mem080_i_mem_prty mem081_i_mem_prty mem082_i_mem_prty mem083_i_mem_prty mem093_i_mem_prty mem094_i_mem_prty mem095_i_mem_prty mem084_i_mem_prty mem085_i_mem_prty mem086_i_mem_prty mem087_i_mem_prty mem088_i_mem_prty mem079_i_mem_prty mem099_i_mem_prty mem100_i_mem_prty mem096_i_mem_prty mem097_i_mem_prty mem098_i_mem_prty mem101_i_mem_prty mem102_i_mem_prty mem108_i_mem_prty mem031_ext_i_mem_prty mem034_ext_i_mem_prty vmain_por_assert vmain_por_deassert perst_assert perst_deassert otp_ecc_ded_0 otp_ecc_ded_1 otp_ecc_ded_2 otp_ecc_ded_3 otp_ecc_ded_4 otp_ecc_ded_5 otp_ecc_ded_6 otp_ecc_ded_7 fake_par_err tx_overflow_0 tx_underflow_0 tx_overflow_1 tx_underflow_1 tx_overflow_2 tx_underflow_2 tx_overflow_3 tx_underflow_3 ln0_at_10M ln0_at_100M ln1_at_10M ln1_at_100M ln2_at_10M ln2_at_100M ln3_at_10M ln3_at_100M ln0_an_resolve_50g_cr2 ln0_an_resolve_50g_kr2 ln0_an_resolve_40g_cr4 ln0_an_resolve_40g_kr4 ln0_an_resolve_25g_gr ln0_an_resolve_25g_cr ln0_an_resolve_25g_kr ln0_an_resolve_10g_kr ln0_an_resolve_1g_kx ln1_an_resolve_50g_cr2 ln1_an_resolve_50g_kr2 ln1_an_resolve_40g_cr4 ln1_an_resolve_40g_kr4 ln1_an_resolve_25g_gr ln1_an_resolve_25g_cr ln1_an_resolve_25g_kr ln1_an_resolve_10g_kr ln1_an_resolve_1g_kx ln2_an_resolve_50g_cr2 ln2_an_resolve_50g_kr2 ln2_an_resolve_40g_cr4 ln2_an_resolve_40g_kr4 ln2_an_resolve_25g_gr ln2_an_resolve_25g_cr ln2_an_resolve_25g_kr ln2_an_resolve_10g_kr ln2_an_resolve_1g_kx ln3_an_resolve_50g_cr2 ln3_an_resolve_50g_kr2 ln3_an_resolve_40g_cr4 ln3_an_resolve_40g_kr4 ln3_an_resolve_25g_gr ln3_an_resolve_25g_cr ln3_an_resolve_25g_kr ln3_an_resolve_10g_kr ln3_an_resolve_1g_kx avs_irq fuse_stat_corrupted meansmem_perr binmem_perr